Feature request:Ability to edit hierarchical port labels AFTER initial hierarchical schematic creation

I’m finding that if I add ports to a hierarchical symbol, create a schematic and I then want to add ADDITIONAL ports to a symbol LATER on then the labels can not be added retrospectively.
I have to copy the entire schematic that has any new net labels added to the clipboard and save the schematic with a new name. I then have to RECREATE the new hierarchical symbol with any additional added ports that correspond to the new labels and point it to a new EMPTY schematic and then paste the clipboard contents to the EMPTY schematic. This is a bit awkward if I have only added ONE additional net label to my schematic. It would be nice if I could ADD hierarchical ports from WITHIN a schematic. I hope this explanation is clear. Please ask if you need any clarification. Thanks.

For hierarchical symbols and schematics, you can just add/remove/rename pins on the symbol right on the schematic. The pin names connect to the netnames in the lower-level schematic.

Much more awkward is dealing with symbols that netlist against subcircuits expressed as netlists instead of schematics. There, only the pin order makes any difference and not the pin names. You have a problem if you want to edit such a symbol if the netlist changes and, if you’re not comfortable with it, it’s less error-prone to simply regenerate the symbol.

Also difficult is if you want to change the pinout of a .DLL device. In principle, you can edit the main module template, but it’s safer to save the .cpp(or .v) in an ASCII editor(QUX.exe includes what you need) and the regenerate the evaluation template anew to match the new pinout and paste your code back into the evaluation function body.

I don’t want to do that for you because my experience with all these automatic code generating IDEs is that while they work out well enough for initial boilerplate generation, eventually they mess things up to point that’s hard to recover from.


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