Timestep too small during .tran, normally represent convergence failure in numerical calculation, where result may oscillating or not within error limit.
abstol : Absolute current error tolerance
vntol : Absolute voltage error tolerance
cshunt : Capacitance added from every node to ground
In your example, your circuit can convert with one of this .option (if nothing change in your schematic)
- .option cshunt=1p
- OR .option vntol=5e-1 (with fast math disable)
Adding capacitance allows the simulation to converge by providing a ground path for high-frequency oscillations or numerical noise.
Reducing vntol (I do not recommend this, 5e-1 is quite large) allows for more error in determining a converged result.
abstol seems not critical in your example, but again, this is to allow more error in current and help converge
Read this Hspice user guide, section 14, title : Troubleshooting ‘Time step Too Small’ Errors. It explains several common approach in handling timestep too small in spice simulation.
HSPICE User Guide: Simulation and Analysis (ucsd.edu)
I also leave a similar note in this post
Scripting in Qspice - QSPICE - Qorvo Tech Forum