Fatal error: Timestep too small, full bridge dc-dc series resonant converter

Hi,

I am simulating this below circuit:
Example21.qsch (21.7 KB)

When Fsw is 100kHz and 200kHz the simulation runs ok, without error.

But when Fsw is between 100kHz and 200kHz qspice simulation throw this error:
Fatal error: Timestep too small(1.04167e-17) at t=0.000729034

Fsw=100kHz:
image
Ok

Fsw=200kHz:
image
Ok

Fsw between 100kHz<Fsw<200kHz, example with Fsw=150kHz:
image

image
Not Ok

I do not understand why when switching frequency (Fsw) is between 100kHz and 200kHz qspice simulation throw me this timestep too small error, and how to resolve it. It should be like that?

Resonant frequency of this circuit is:

1/(2pisqrt(1uH*1uF)) = 159.155kHz

Fsw=110kHz:
image
image
Plot looks pretty good, but simulation runs only till ~1.3ms (this is whem fatal error: timestep too small is occuring), but simulation should run till 30ms.

Is still this (by putting in parallel a 1nF/1pF cap at each switch and at bridge rectifier diode (right)) approach the right approach in order to avoid this timestep to small error in this case of circuits?

Now seems to look pretty ok:



See


Example21AB.qsch (21.8 KB)

Hm, what does these options abstol and cshunt in such a way that this time step to small to dissapear?

Timestep too small during .tran, normally represent convergence failure in numerical calculation, where result may oscillating or not within error limit.

abstol : Absolute current error tolerance
vntol : Absolute voltage error tolerance
cshunt : Capacitance added from every node to ground

In your example, your circuit can convert with one of this .option (if nothing change in your schematic)

  • .option cshunt=1p
  • OR .option vntol=5e-1 (with fast math disable)

Adding capacitance allows the simulation to converge by providing a ground path for high-frequency oscillations or numerical noise.
Reducing vntol (I do not recommend this, 5e-1 is quite large) allows for more error in determining a converged result.

abstol seems not critical in your example, but again, this is to allow more error in current and help converge

Read this Hspice user guide, section 14, title : Troubleshooting ‘Time step Too Small’ Errors. It explains several common approach in handling timestep too small in spice simulation.
HSPICE User Guide: Simulation and Analysis (ucsd.edu)

I also leave a similar note in this post
Scripting in Qspice - QSPICE - Qorvo Tech Forum

3 Likes

You can also run your circuit without extra .option or capacitance, but by smoothing diode I-V curve with epsilon, e.g.
.model D D Ron=1m Roff=100Meg VFWD=0.7 epsilon=0.1

Mike hosted a Webinar on 5-Sept-2024, where he explained how SPICE solves circuits and the key aspects you need to know to help your circuit converge. By reviewing this explanation, you will understand why adding capacitance across your switch/diode will be beneficial.

From 1h15m53s to 1h24m15s

2 Likes