When did a dc analysis, QSPICE output window:
Schematic as below
Any options to modify iteration issue?
Why you use .dc?
No idea how .dc can help for modelling this.
I usually use .tran with V1 as PWL and voltage parameter stepping for such circuits.
It’s OK when using pwl source with .tran command.
Do you know why .dc has above issue, but .tran without it.