Error / bug linked to library file with multiple .lib .endl entries


I am simulating a schematic which contains following .lib statement with a ‘tm’ [ENTRY] parameter:

.lib .\spice_models\mos.lib tm

The mos.lib file which is referenced contains several .lib .endl entries (see it at the end of this message).
With the “.lib .\spice_models\mos.lib tm” statement, Qspice gives following error:

Fatal error: Could not open file “ff”

Note that the ff section directly follows the tm section in the mos.lib file

However, if using “.lib .\spice_models\mos.lib ss” statement in the schematic (instead of tm), there is no error. I attribute that to the fact that ss section is the last in the mos.lib file.


mos.lib file

.lib tm
.inc .\spice_models\xt018\models\mos\tm_mos.mod
.inc .\spice_models\xt018\models\mos\ne.mod
.inc .\spice_models\xt018\models\mos\pe.mod

.lib ff
.inc .\spice_models\xt018\models\mos\wp_mos.mod
.inc .\spice_models\xt018\models\mos\ne.mod
.inc .\spice_models\xt018\models\mos\pe.mod

.lib ss
.inc .\spice_models\xt018\models\mos\ws_mos.mod
.inc .\spice_models\xt018\models\mos\ne.mod
.inc .\spice_models\xt018\models\mos\pe.mod

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Hello, have you been able to make any progress in this?
I am in a similar situation. I am trying to make use of the GF180 open source pdk (available on github) to design in qspice. I have made some modifications to those model files (in combining them & making the corner calls simpler) and have successfully utilised the pdk in designing circuits with various mosfets(modified to X (subckt) type) and bjts and simulating the process corners & monte carlo as well.

The reason I’m trying this again in QSpice is, because also models semiconductor passive devices(resistors & caps), but ltspice cannot and secondarily the additional features of qspice. But, I’ve not been able to succeed in using the pdk in qspice. It is a giving the same error as above. In my case, there is a single model file with all the .lib libraries and nested .lib calls. See the below images.
The corner libraries(typ,ff,ss,mc) are called through the “.lib PATH [entry]” directive’s entry parameter, the corner libraries then call different libraries of device types(mos,bjt,res,cap,etc) associated with that corner, which in turn call the particuar device instantiated (mos3v3, mos6v0,etc).

In the schematic, I’ve used 3.3V nmos, and called the typical corner (renamed ‘0’ for convenience). I feel that the simulator successfully identified the device and corner and entered the ‘.LIB 0’ library and then into the ‘.LIB typical’ library and then successfully understood that it needs to go into the ‘.lib nfet_03v3_t’ library, but is unable to.

I assume there is no limit to the nesting depth of .lib statements. Someone please help.

Adding link to other images including the test schematic, since only 1 image is allowed in this post.
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