DWM3001CDK 1:2 SS‑TWR Ranging: Second Anchor Fails RX Frame Checksum

The “good” status register comes out as 0x03806ff7, whereas the problematic one is 0x03a000f7. Digging deeper, I found the following key difference:

  • Difference:
    • In the normal case, both the RXFCG (0x4000) and RXFR (0x2000) bits are set, indicating that the preamble and CRC checks both passed.
    • In the failing case, the RXPTO (0x200000) flag is set, which means a “preamble timeout” occurred.

In other words, on the second device (ID 101) the preamble isn’t being detected correctly, so DWT_INT_RXPTO_BIT_MASK is triggered and the code never even reaches the CRC stage—hence the failure.


I’m not sure whether this is a timing/delay issue or a misconfiguration of those flags. I’ve already tried increasing these values without any change:

sit_set_rx_after_tx_delay(DS_RESP_TX_TO_FINAL_RX_DLY_UUS);
sit_set_rx_timeout(DS_FINAL_RX_TIMEOUT + 2000);
sit_set_preamble_detection_timeout(DS_PRE_TIMEOUT + …);