Hi all,
I have some DWM1000 ICs and I have some troubles with the SPI communication. In the DWM1000 Datasheet, it is written: “GPIO 5/ 6 are sampled / latched on the rising edge of the RSTn pin to determine the SPI mode. They are internally pulled low to configure a default SPI mode 0 without the use of external components.” (CPOL = 0, CPHA = 0).
However, I recorded a transaction where my SPI master sent 0x00 (i.e read memory address 0x00, DEV ID) and clocked SCK to get 4 bytes at the MISO, expecting values “0x30 0x01 0xca 0xde”. You will find in attachment a figure of SCK and MISO during that transaction. If we take the MISO values on the rising edge, we have the expected DEV ID, but the values are not launched on the falling edge but right after the rising edge. Is it an expected behavior from that IC?
Best regards,
Cedric