I’m trying to make the examples work on my custom pcb board with the DWM1000 chips.
The example “ex_01a_simple_tx” + “ex_02a_simple_rx” works for me. That means I see in debug mode that the board with the “ex_02a_simple_rx” checks for the “status_reg & SYS_STATUS_RXFCG” and says that a frame has been received.
When I try to run the “ex_05a_ds_twr_init” + “ex_05b_ds_twr_resp” the 05b checks as well for the “status_reg & SYS_STATUS_RXFCG” but there is no frame and it goes for the else to clear RX errors/timeouts. Same problem occurs with the “ex_06a” + “ex_06b”. I checked the application note APS013 and it says, that there is a discovery phase + ranging phase. I don’t see the discovery phase in ex_05 neither in ex_06… am I missing something or is it not necessary?
I would appreciate any tips or help.
Hi @Claus_CE ,
Standard DS TWR needs only 3 messages between initiator and responder: Poll + Resp + Final
I guess discovery phase was documented in the context of mdek1001.
This should be extra phase in the context of RTLS developement.
thank you for your reply. Alright that means the examples should work out of the box.
Then I still have a problem with the examples because I see on my EVK1000 DevKit which is connected to my pc with decaranging for displaying any packages that the examples send data via UWB.
My problem that I don’t understand is that none of the examples work out of the box… e.g. the 03a+03b example:
a: sends a frame out
b: receives the frame and should respond to that frame
b responses only when I insert a delay of 20-30ms between reading the frame into my buffer and sending a response out. If the delay is too short the response gets irregular and occurs only every 2-3 receptions.
What am I missing?
In ex05 and ex06 something similar happens and I really don’t understand why the communication won’t work with the given examples. May it be a problem with my clock speed? I have sysclk, ahb and apb clocks at HSI 16 MHz.