DW3000 VDD2A/B Internal Power Distribution

We would like to implement our own custom “development board” for the DW3000 transceiver and while looking at the datasheet, a curiosity about the internal power distribution emerged and can be summarized as:

  1. Is there a performance gain to be had from powering VDD2B from a DC/DC converter due to the higher power consumption of the TX RF block, and using a low noise (with good layout isolation and filtering) LDO for VDD2A since it seems it only powers the clock block and the OTP? (referencing Figure 31 from the DW3000 DS)

  2. And as a secondary point, for using a TCXO (required in our case for operation over a wide temperature range) the datasheet specifies VDD2 as the maximum input voltage level, which sounds as if it actually means VDD2A as that powers (through internal LDO) the XTAL_OSC block which would also contain the first circuitry encountered by the TCXO’s clock. Would it be fair then to assume that VDD2A should therefore be treated with the same or similar care as the supply for the TCXO itself? Would a noisy VDD2A affect the phase noise performance of the TCXO?
    (This sounds like the explicit requirement regarding the VBAT and TCXO powering scheme found on the DW1000, but it is no longer enforced here apart from the datasheet recommending a ferrite bead on VDD2A)

Any help regarding any of the points is highly appreciated.

Thank you and Best regards,

Hi @flupas
re 1) please take a look at these pictures: https://www.qorvo.com/products/d/da008142 - chapter 6.1

re 2) More or less the answer is yes noisy signal on VDD2 and VDD3 can affect phase noise. However I would recommend to follow application diagram (chapter 7.1). However the DW3K is less sensitive to noise than the DW1K - but it is hard to say how much.