Hey,
We are currently doing research with the DW1000 (working with it has been a real pleasure so far!).
However we encountered some weird behavior with the carrier frequency offsets, as can be seen in the attached image (raw carrier frequency offsets reading are marked in blue)
Please ignore the plot titles, its just three different experiments with different parameters, however they do not have any influence on the carrier frequency offsets we observe. Indeed, while not plotted in the attached images, if one calculates the frequency offset through DSTWR, the values agree with the CFO reading. The problem now is that, as can also be seen in the images, the rapid changes in the frequency offset will create a few outlier measurements which are a little bit worse than expected Actually, this is not a too big problem for us, we are just curious whether this is known behaviour or caused by a driver misconfiguration? (We observed this behaviour in two independent driver implementations, one in zephyr and the other one in contiki)
Since the post edit feature does not work for me, I add more information here in a reply. Please also ignore that the distribution of ranging measurements widens with increasing sample count, this is due to another experiment where we gradually increase the delay durations and has nothing to do with the CFOs. The outliers I referenced above are the few outlier samples right at the rapid CFO changes.
What is your DW1000 clock source and physical setup like? Any chance that the 38.4 MHz clock is experiencing jumps in frequency? Either sudden airflow over a crystal or a tcxo that implements it’s temperature compensation digitally?
If you put everything in a sealed box do these events become rarer over time as temperature stabalies?
The two drivers you used are probably based on the same underlying code, either directly or by re-implementing the same features in the same way for a different platform. Either way until you’ve dug into the code to verify they use difference code to determine how to configure the unit I would work on the assumption that they are in effect identical.
Ultimately for real world applications this sort of thing doesn’t matter as long as it’s not too frequent. You’re going to get weird range outliers from all sorts of difference causes, if your higher level application can’t cope with that then it’s not going to work well. As such from a product point of view it’s not a big issue. However I appreciate that in a more controlled research type environment it’s nice to eliminate this sort of thing.
DW1000 can have different clock source types such as Xtal or External Clock sources(TCXO, OCXO etc.).
The rapid changes in frequency might be due to rapid changes in temperature or vibration.
It would be a nice experiment if you generate a CW signal and monitor the frequency by using a spectrum analyser or frequency counter. You can vibrate or place a fan next to it to change environmental conditions to see the possible jumps in frequency.
Moreover, the DSTWR algorithm should be able to compensate for any frequency offsets up to 40ppm. Maybe, abrupt changes in frequency also affect the quality of modulation and receiver performance.
I would advise to filter outliers by using a post-processing algorithm.
Thanks for doing this experiment and let us know if you have any updates or questions.
