Yes sorry, those are multiple packets after another. Each major peak is one packet.
Regarding XTAL-OTP: Do you mean LDOTUNE? This is basically all the setup I am doing:
DEV_ID = self.read(reg_addr=0x00, sub_reg_addr=0x00, len=4)
print(
f"Device-ID: REV: {DEV_ID[0] & 0x0F}, VER: {DEV_ID[0] >> 3}, MODEL: {DEV_ID[1]}, RIDTAG: {hex(DEV_ID[3] << 8 | DEV_ID[2])}")
self.write(reg_addr=0x23, sub_reg_addr=0x04, data=[0x70, 0x88])
AGC_TUNE1 = self.read(reg_addr=0x23, sub_reg_addr=0x04, len=2)
print(f"Modified AGC_TUNE1 to {hex(AGC_TUNE1[1] << 8 | AGC_TUNE1[0])}")
self.write(reg_addr=0x23, sub_reg_addr=0x0C, data=[0x07, 0xA9, 0x02, 0x25])
AGC_TUNE2 = self.read(reg_addr=0x23, sub_reg_addr=0x0C, len=4)
print(
f"Modified AGC_TUNE2 to {hex(AGC_TUNE2[3] << 24 | AGC_TUNE2[2] << 16 | AGC_TUNE2[1] << 8 | AGC_TUNE2[0])}")
self.write(reg_addr=0x23, sub_reg_addr=0x12, data=[0x35, 0x00])
AGC_TUNE3 = self.read(reg_addr=0x23, sub_reg_addr=0x12, len=2)
print(f"Modified AGC_TUNE3 to {hex(AGC_TUNE3[1] << 0 | AGC_TUNE3[0])}")
self.write(reg_addr=0x27, sub_reg_addr=0x00, data=[0x01, 0x00])
DRX_TUNE0b = self.read(reg_addr=0x27, sub_reg_addr=0x00, len=2)
print(f"Modified DRX_TUNE0b to {hex(DRX_TUNE0b[1] << 8 | DRX_TUNE0b[0])}")
self.write(reg_addr=0x27, sub_reg_addr=0x04, data=[0x87, 0x00])
DRX_TUNE1a = self.read(reg_addr=0x27, sub_reg_addr=0x04, len=2)
print(f"Modified DRX_TUNE1a to {hex(DRX_TUNE1a[1] << 8 | DRX_TUNE1a[0])}")
self.write(reg_addr=0x27, sub_reg_addr=0x06, data=[0x10, 0x00])
DRX_TUNE1b = self.read(reg_addr=0x27, sub_reg_addr=0x06, len=2)
print(f"Modified DRX_TUNE1b to {hex(DRX_TUNE1b[1] << 8 | DRX_TUNE1b[0])}")
self.write(reg_addr=0x27, sub_reg_addr=0x08, data=[0x2D, 0x00, 0x1A, 0x31])
DRX_TUNE2 = self.read(reg_addr=0x27, sub_reg_addr=0x08, len=4)
print(
f"Modified DRX_TUNE2 to {hex(DRX_TUNE2[3] << 24 | DRX_TUNE2[2] << 16 | DRX_TUNE2[1] << 8 | DRX_TUNE2[0])}")
self.write(reg_addr=0x27, sub_reg_addr=0x26, data=[0x10, 0x00])
DRX_TUNE4H = self.read(reg_addr=0x27, sub_reg_addr=0x26, len=2)
print(f"Modified DRX_TUNE4H to {hex(DRX_TUNE4H[1] << 8 | DRX_TUNE4H[0])}")
self.write(reg_addr=0x2E, sub_reg_addr=0x0806, data=[0x3D])
NTM = self.read(reg_addr=0x2E, sub_reg_addr=0x0806, len=1)
print(f"Modified NTM to {hex(NTM[0])}")
self.write(reg_addr=0x2E, sub_reg_addr=0x1806, data=[0x07, 0x16])
LDE_CFG2 = self.read(reg_addr=0x2E, sub_reg_addr=0x1806, len=2)
print(f"Modified LDE_CFG2 to {hex(LDE_CFG2[1] << 8 | LDE_CFG2[0])}")
self.write(reg_addr=0x1E, sub_reg_addr=0x00, data=[0x48, 0x28, 0x08, 0x0E])
TX_POWER = self.read(reg_addr=0x1E, sub_reg_addr=0x00, len=4)
print(f"Modified TX_POWER to {hex(TX_POWER[3] << 24 | TX_POWER[2] << 16 | TX_POWER[1] << 8 | TX_POWER[0])}")
self.write(reg_addr=0x28, sub_reg_addr=0x0C, data=[0xE3, 0x3F, 0x1E, 0x00])
RF_TXCTRL = self.read(reg_addr=0x28, sub_reg_addr=0x0C, len=4)
print(
f"Modified RF_TXCTRL to {hex(RF_TXCTRL[3] << 24 | RF_TXCTRL[2] << 16 | RF_TXCTRL[1] << 8 | RF_TXCTRL[0])}")
self.write(reg_addr=0x2A, sub_reg_addr=0x0B, data=[0xB5])
TC_PGDELAY = self.read(reg_addr=0x2A, sub_reg_addr=0x0B, len=1)
print(f"Modified TC_PGDELAY to {hex(TC_PGDELAY[0])}")
self.write(reg_addr=0x2B, sub_reg_addr=0x07, data=[0x1D, 0x04, 0x00, 0x08])
FS_PLLCFG = self.read(reg_addr=0x2B, sub_reg_addr=0x07, len=4)
print(
f"Modified FS_PLLCFG to {hex(FS_PLLCFG[3] << 24 | FS_PLLCFG[2] << 16 | FS_PLLCFG[1] << 8 | FS_PLLCFG[0])}")
self.write(reg_addr=0x2B, sub_reg_addr=0x0B, data=[0xBE])
FS_PLLTUNE = self.read(reg_addr=0x2B, sub_reg_addr=0x0B, len=1)
print(f"Modified FS_PLLTUNE to {hex(FS_PLLTUNE[0])}")
EC_CTRL = self.read(reg_addr=0x24, sub_reg_addr=0x00, len=4)
EC_CTRL[0] |= (1 << 2) # Clock PLL lock detect
self.write(reg_addr=0x24, sub_reg_addr=0x00, data=EC_CTRL)
# PLL Config
RF_CONF = self.read(reg_addr=0x28, sub_reg_addr=0x00, len=4)
RF_CONF[1] |= (1 << 7) | (1 << 6) | (1 << 5) # Enable CLK_PLL and RF_PLL
# RF_CONF[2] |= (1 << 5) # Configure for RX
self.write(reg_addr=0x28, sub_reg_addr=0x00, data=RF_CONF)
# Set LDELOAD for timestamp information as Receiver according to 2.5.5.10
PMSC_CTRL0 = self.read(reg_addr=0x36, sub_reg_addr=0x00, len=4)
OTP_CTRL = self.read(reg_addr=0x2D, sub_reg_addr=0x06, len=2)
PMSC_CTRL0[0] = 0x01
PMSC_CTRL0[1] = 0x03
OTP_CTRL[0] = 0x00
OTP_CTRL[1] = 0x80
self.write(reg_addr=0x36, sub_reg_addr=0x00, data=PMSC_CTRL0)
self.write(reg_addr=0x2D, sub_reg_addr=0x06, data=OTP_CTRL)
time.sleep(0.01)
PMSC_CTRL0 = self.read(reg_addr=0x36, sub_reg_addr=0x00, len=4)
PMSC_CTRL0[0] = 0x00
PMSC_CTRL0[1] = 0x02
self.write(reg_addr=0x36, sub_reg_addr=0x00, data=PMSC_CTRL0)
# Check if LDOTUNE was calibrated according to 6.3.3
self.write(reg_addr=0x2D, sub_reg_addr=0x04, data=[0x04, 0x00])
self.write(reg_addr=0x2D, sub_reg_addr=0x06, data=[0x03])
self.write(reg_addr=0x2D, sub_reg_addr=0x06, data=[0x00])
OTP_LDOTUNE = self.read(reg_addr=0x2D, sub_reg_addr=0x0A, len=4)
if OTP_LDOTUNE[0] != 0:
self.write(reg_addr=0x28, sub_reg_addr=0x30, data=OTP_LDOTUNE)
OTP_LDOTUNE = self.read(reg_addr=0x28, sub_reg_addr=0x30, len=4)
print(
f"Modified LDOTUNE to {hex(OTP_LDOTUNE[3] << 24 | OTP_LDOTUNE[2] << 16 | OTP_LDOTUNE[1] << 8 | OTP_LDOTUNE[0])}")
else:
print("LDOTUNE value has not been set.")