DW1000 + MCP2210: Poor Communication Range

[inancinan]

We developed a Linux application to evaluate DW1000 transmit / receive range and APIs. We are using two EVK1000 boards in external SPI mode together with an MCP2210 adapter board to do the USB / SPI conversion. The linux application talks to DW1000 via USB MCP2210 HID library (https://github.com/kerrydwong/MCP2210-Library). We have no problems in reading / writing to DW1000 SPI with one exception #4 as listed below.

We ported sample application code in DW1000 API examples into our Linux application, essentially example_1a_simpletx and example_2a_simplerx. dwt_initialise, dwt_configure, and corresponding transmit/receive APIs in the decawave library are all ported and functions in the exact same way.

We observe following problems with our implementation when one EVK board is set to transmit and the other is set to receive. We configure and test the radios at operational modes 3 and 5 as listed in EVK manual Table 3.

1. Poor communication range: We confirmed that the transmitter is transmitting at about -11dBm (±2dBm). Still the maximum communication range is about 5m irrespective of the operational mode. Beyond that the receiver would not report any received packets (no errors, no preamble detection etc.). As suggested in another thread and the user manual, we carried out crystal trimming, but the range improvement was unobservable even when the crystal freq closely match between boards. We suspect some major receiver initialization / configuration problem, but not sure what can be missing given we ported the example code and corresponding library functions ‘almost’ as is (see #2 and #3 on ‘almost’ comment).

2. Soft reboot kills SPI: We had to comment out dwt_softreset call in dwt_initialise function as a soft reset kills all radio SPI communication, and the radio will all return 0xFF value for all reads.

3. Hard reset at boot: We cannot carry out reset_DW1000 in the main function as we do not have control of GPIO reset line. Is this reset necessary at boot? If yes, can it be executed on the EVK via other means? For now, we reset the transceiver via Register 0xD write at TRXOFF mask instead of a hard reset.

4. Payload buffer programming: Register 0x9 contents (i.e. payload) cannot be programmed. The buffer will always report some junk hexadecimal number for all offset values. The value will differ at every boot, but the value read is same for all offset no matter what value we program at the corresponding byte offset.

Example ST MCU code executes some functionality we cannot implement via our SPI only interface (e.g., hard reset). Are hard reset and soft reboot necessary? Would these missing lead to improper receiver configuration/initialization and poor communication range?

The EVK boards seem to operate at much longer range with the ranging demo binary programmed on them. Can this binary be compiled from the sample code online? So that we reprogram the boards with a binary compiled from a known source code and use this code, initialization/configuration routines as baseline.

[zoran_skrba]

I am thinking the SPI comms between the DW1000 and your MCU are bad, please check mode, freq, etc. Please verify the read/write are working correctly. If the SPI comms are not 100% then all else is pointless.

[Brainstation23]

iSP problem . as your details

[inancinan]

@zoran skrba

I am thinking the SPI comms between the DW1000 and your MCU are bad, please check mode, freq, etc. Please verify the read/write are working correctly. If the SPI comms are not 100% then all else is pointless.

Hi Zoran,

SPI comms seem to be running fine. We checked the bus with a logic analyzer and no anomalies observed. The bytes are intact. We operate SPI at 1MHz, mode 2. Read/Write are verified to be working correctly. I am copying two debug traces, one from transmitter and one from receiver. You will see continuous read back from accessed registers to confirm the writes.

The radio configuration is as follows: Payload (10 bytes + 2 byte CRC)

dw1000.conf.prf             = DW_PRF_16_MHZ; 
dw1000.conf.channel         = DW_CHANNEL_5;
dw1000.conf.preamble_length = DW_PREAMBLE_LENGTH_1024; 
dw1000.conf.preamble_code   = DW_PREAMBLE_CODE_3; 
dw1000.conf.pac_size        = DW_PAC_SIZE_32;
dw1000.conf.sfd_type        = DW_SFD_NON_STANDARD;
dw1000.conf.data_rate       = DW_DATA_RATE_110_KBPS; 

The debug trace format:

Read/Write : Operation Type
: Register Address
: Only Present when it is a multiple octet header
: Read/write Length in bytes
: Actual header bytes on SPI bus, only Present when it is a multiple octet header
: Data Read or Written in the order the bytes appear on SPI

Immediate observations from traces:
[list=1]
[]Register 28:0C Byte 3 is always 0xDE even if we write 0x00, see transmitter/receiver trace in bold.
[]Register 09 writes are not accepted, see transmitter trace in bold.
[/list]
Initialisation and configuration function start/end is marked with corresponding text. Please review and see if we are writing some register with incorrect values for the above configuration. Any initilization/configuration missing for proper functionality? Anything done in incorrect order? The traces are when transmitter and receiver are in close vicinity on a desk. If moved apart, the receiver will not receive transmitter’s packet unlike the trace below, and register 0x0f will continue reading all zeroes.

TRANSMITTER:

Read 00 Len 4 Data 30 01 ca de
Read 0d Len 4 Data 00 00 00 00
Write 0d Len 4 Data 40 00 00 00
Initialise Start.
Read 36 Len 2 Data 00 02
Write 36 00 Len 1 Cmd f600 Data 01
Write 36 01 Len 1 Cmd f601 Data 02
Write 24 Len 1 Data 04
Write 2d 04 Len 2 Cmd ed04 Data 1e 00
Write 2d 06 Len 1 Cmd ed06 Data 01
Write 2d 06 Len 1 Cmd ed06 Data 02
Read 2d 0a Len 4 Cmd 6d0a Data 00 00 00 00
Write 2d 06 Len 1 Cmd ed06 Data 00
Write 2d 04 Len 2 Cmd ed04 Data 04 00
Write 2d 06 Len 1 Cmd ed06 Data 01
Write 2d 06 Len 1 Cmd ed06 Data 02
Read 2d 0a Len 4 Cmd 6d0a Data 14 01 00 00
Write 2d 06 Len 1 Cmd ed06 Data 00
Write 2d 12 Len 1 Cmd ed12 Data 02
Write 2b 0e Len 1 Cmd eb0e Data 70
Write 36 00 Len 2 Cmd f600 Data 01 03
Write 2d 06 Len 2 Cmd ed06 Data 00 80
Write 36 00 Len 2 Cmd f600 Data 00 02
Read 36 Len 2 Data 00 02
Write 36 00 Len 1 Cmd f600 Data 00
Write 36 01 Len 1 Cmd f601 Data 02
Write 2c 0a Len 1 Cmd ec0a Data 00
Initialise End.
Read 04 Len 4 Data 00 12 40 00
Read 08 Len 4 Data 0c 80 09 00
Read 1f Len 4 Data 55 00 c7 18
Configuration Start.
Write 04 Len 4 Data 00 12 40 00
Write 2e 2804 Len 2 Cmd ee8404 Data 3d 0a
Write 2e 806 Len 2 Cmd ee8606 Data 6d 00
Write 2e 1806 Len 2 Cmd ee8606 Data 07 16
Write 2b 07 Len 4 Cmd eb07 Data 1d 04 00 08
Write 2b 0b Len 1 Cmd eb0b Data be
Write 28 0b Len 1 Cmd e80b Data d8
Write 28 0c Len 4 Cmd e80c Data e0 3f 1e 00
Write 27 02 Len 2 Cmd e702 Data 16 00
Write 27 04 Len 2 Cmd e704 Data 87 00
Write 27 06 Len 2 Cmd e706 Data 20 00
Write 27 26 Len 2 Cmd e726 Data 28 00
Write 27 08 Len 4 Cmd e708 Data 9a 00 1a 35
Write 23 04 Len 2 Cmd e304 Data 70 88
Write 23 0c Len 4 Cmd e30c Data 07 a9 02 25
Write 1f Len 4 Data 55 00 c7 18
Write 08 Len 4 Data 0c 80 09 00
Read 0d Len 4 Data 00 00 00 00
Write 0d Len 4 Data 42 00 00 00
Read 26 Len 4 Data 00 00 05 de
Write 26 Len 4 Data 00 00 05 de
Read 26 Len 4 Data 00 00 05 de
Write 1e Len 4 Data 48 28 08 0e
Write 2a 0b Len 1 Cmd ea0b Data c0
Configuration End.
Read 00 Len 4 Data 30 01 ca de
Initialising device: 3737780528
Conf Read Start.
Read 04 Len 4 Data 00 12 40 00
Read 08 Len 4 Data 0c 80 09 00
Read 1f Len 4 Data 55 00 c7 18
Read 23 04 Len 2 Cmd 6304 Data 70 88
Read 23 0c Len 4 Cmd 630c Data 07 a9 02 25
Read 23 12 Len 2 Cmd 6312 Data 35 00
Read 27 02 Len 2 Cmd 6702 Data 16 00
Read 27 04 Len 2 Cmd 6704 Data 87 00
Read 27 06 Len 2 Cmd 6706 Data 20 00
Read 27 08 Len 4 Cmd 6708 Data 9a 00 1a 35
Read 27 26 Len 2 Cmd 6726 Data 28 00
Read 28 0b Len 1 Cmd 680b Data d8
Read 28 0c Len 4 Cmd 680c Data e0 3f 1e de
Read 2a 0b Len 1 Cmd 6a0b Data c0
Read 2b 07 Len 4 Cmd 6b07 Data 1d 04 00 08
Read 2b 0b Len 1 Cmd 6b0b Data be
Conf Read End.
Transmit Start.
Write 09 Len 10 Data c5 00 44 45 43 41 57 41 56 45
Read 09 Len 10 Data 87 87 87 87 87 87 87 87 87 87
Read 08 Len 4 Data 0c 80 09 00
Write 08 Len 4 Data 0c 80 09 00
Read 0d Len 4 Data 00 00 00 00
Write 0d Len 4 Data 02 00 00 00
Read 0f Len 5 Data f2 00 80 02 00
Packet Sent!

RECEIVER:

Read 00 Len 4 Data 30 01 ca de
Read 0d Len 4 Data 00 00 00 00
Write 0d Len 4 Data 40 00 00 00
Initialise Start.
Read 36 Len 2 Data 00 02
Write 36 00 Len 1 Cmd f600 Data 01
Write 36 01 Len 1 Cmd f601 Data 02
Write 24 Len 1 Data 04
Write 2d 04 Len 2 Cmd ed04 Data 1e 00
Write 2d 06 Len 1 Cmd ed06 Data 01
Write 2d 06 Len 1 Cmd ed06 Data 02
Read 2d 0a Len 4 Cmd 6d0a Data 00 00 00 00
Write 2d 06 Len 1 Cmd ed06 Data 00
Write 2d 04 Len 2 Cmd ed04 Data 04 00
Write 2d 06 Len 1 Cmd ed06 Data 01
Write 2d 06 Len 1 Cmd ed06 Data 02
Read 2d 0a Len 4 Cmd 6d0a Data 11 01 00 00
Write 2d 06 Len 1 Cmd ed06 Data 00
Write 2d 12 Len 1 Cmd ed12 Data 02
Write 2b 0e Len 1 Cmd eb0e Data 70
Write 36 00 Len 2 Cmd f600 Data 01 03
Write 2d 06 Len 2 Cmd ed06 Data 00 80
Write 36 00 Len 2 Cmd f600 Data 00 02
Read 36 Len 2 Data 00 02
Write 36 00 Len 1 Cmd f600 Data 00
Write 36 01 Len 1 Cmd f601 Data 02
Write 2c 0a Len 1 Cmd ec0a Data 00
Initialise End.
Read 04 Len 4 Data 00 12 40 00
Read 08 Len 4 Data 0c 80 09 00
Read 1f Len 4 Data 55 00 c7 18
Configuration Start.
Write 04 Len 4 Data 00 12 40 00
Write 2e 2804 Len 2 Cmd ee8404 Data 3d 0a
Write 2e 806 Len 2 Cmd ee8606 Data 6d 00
Write 2e 1806 Len 2 Cmd ee8606 Data 07 16
Write 2b 07 Len 4 Cmd eb07 Data 1d 04 00 08
Write 2b 0b Len 1 Cmd eb0b Data be
Write 28 0b Len 1 Cmd e80b Data d8
Write 28 0c Len 4 Cmd e80c Data e0 3f 1e 00
Write 27 02 Len 2 Cmd e702 Data 16 00
Write 27 04 Len 2 Cmd e704 Data 87 00
Write 27 06 Len 2 Cmd e706 Data 20 00
Write 27 26 Len 2 Cmd e726 Data 28 00
Write 27 08 Len 4 Cmd e708 Data 9a 00 1a 35
Write 23 04 Len 2 Cmd e304 Data 70 88
Write 23 0c Len 4 Cmd e30c Data 07 a9 02 25
Write 1f Len 4 Data 55 00 c7 18
Write 08 Len 4 Data 0c 80 09 00
Read 0d Len 4 Data 00 00 00 00
Write 0d Len 4 Data 42 00 00 00
Read 26 Len 4 Data 00 00 05 de
Write 26 Len 4 Data 00 00 05 de
Read 26 Len 4 Data 00 00 05 de
Write 1e Len 4 Data 48 28 08 0e
Write 2a 0b Len 1 Cmd ea0b Data c0
Configuration End.
Read 00 Len 4 Data 30 01 ca de
Initialising device: 3737780528
Conf Read Start.
Read 04 Len 4 Data 00 12 40 00
Read 08 Len 4 Data 0c 80 09 00
Read 1f Len 4 Data 55 00 c7 18
Read 23 04 Len 2 Cmd 6304 Data 70 88
Read 23 0c Len 4 Cmd 630c Data 07 a9 02 25
Read 23 12 Len 2 Cmd 6312 Data 35 00
Read 27 02 Len 2 Cmd 6702 Data 16 00
Read 27 04 Len 2 Cmd 6704 Data 87 00
Read 27 06 Len 2 Cmd 6706 Data 20 00
Read 27 08 Len 4 Cmd 6708 Data 9a 00 1a 35
Read 27 26 Len 2 Cmd 6726 Data 28 00
Read 28 0b Len 1 Cmd 680b Data d8
Read 28 0c Len 4 Cmd 680c Data e0 3f 1e de
Read 2a 0b Len 1 Cmd 6a0b Data c0
Read 2b 07 Len 4 Cmd 6b07 Data 1d 04 00 08
Read 2b 0b Len 1 Cmd 6b0b Data be
Conf Read End.
Write 0c Len 2 Data 00 00
Read 04 Len 4 Data 00 12 40 00
Write 04 Len 4 Data 00 12 40 00
Receive Start.
Read 0f 03 Len 1 Cmd 4f03 Data 00
Read 0d Len 4 Data 00 00 00 00
Write 0d Len 4 Data 00 01 00 00
Read 0f Len 5 Data 00 00 00 00 00
Read 0f Len 5 Data 00 00 00 00 00
Read 0f Len 5 Data 00 00 00 00 00
Read 0f Len 5 Data 00 00 00 00 00
Read 0f Len 5 Data 00 2b 00 00 00
Read 0f Len 5 Data 00 2b 00 00 00
Read 10 Len 4 Data 0c 80 b9 36
RX 12
Write 0f Len 5 Data 00 20 02 00 00
Read 0d Len 4 Data 00 00 00 00
Write 0d Len 4 Data 40 00 00 00
Write 0f Len 4 Data 00 2b 00 00
Write 0f 04 Len 1 Cmd cf04 Data 00
Read 0f 03 Len 1 Cmd 4f03 Data 00
Read 0d Len 4 Data 00 00 00 00
Write 0d Len 4 Data 00 01 00 00
Read 0f Len 5 Data 00 00 00 00 00

[zoran_skrba]

Note the TX buffer cannot be read. It is write only register.

How are you powering the DW1000/EVB1000 ?

Decawave have simple tx/rx examples - please check that the SPI coms mach these if you are worried you may be writing something incorrectly.
[hr]
Also note 0x28:0c is a 3 byte register the 4th byte is 0xDE. This is correct.

[inancinan]

@zoran skrba

Note the TX buffer cannot be read. It is write only register.

How are you powering the DW1000/EVB1000 ?

Decawave have simple tx/rx examples - please check that the SPI coms mach these if you are worried you may be writing something incorrectly.
[hr]
Also note 0x28:0c is a 3 byte register the 4th byte is 0xDE. This is correct.

Hi Zoran,

Thanks for your reply and the notes on TX buffer and 0x28:0C registers.

We are powering EVB1000 through the micro USB connector. I will compile the simple tx/rx examples and integrate these application code as is with our MCP2210 driver to rule out any configuration.

Is hard reset of the radio or soft reboot as the applications execute at boot definitely necessary for the radio to function properly? Do you see any initilisation/configuration problems or anything done in incorrect order in the debug traces I sent?

[inancinan]

@inancinan

@zoran skrba

Note the TX buffer cannot be read. It is write only register.

How are you powering the DW1000/EVB1000 ?

Decawave have simple tx/rx examples - please check that the SPI coms mach these if you are worried you may be writing something incorrectly.
[hr]
Also note 0x28:0c is a 3 byte register the 4th byte is 0xDE. This is correct.

Hi Zoran,

Thanks for your reply and the notes on TX buffer and 0x28:0C registers.

We are powering EVB1000 through the micro USB connector. I will compile the simple tx/rx examples and integrate these application code as is with our MCP2210 driver to rule out any configuration.

Is hard reset of the radio or soft reboot as the applications execute at boot definitely necessary for the radio to function properly? Do you see any initilisation/configuration problems or anything done in incorrect order in the debug traces I sent?

So I compiled simple_tx and simple_rx sample code with MCP2210 driver and communication range issue has been resolved. This is good.

One can argue that there is some configuration problem we oversee in the previous application that leads to range problems.

BUT I have two debug traces to compare the results of soft radio reboot and see if you can provide any insights on the different outcome. As debug traces indicate, both apps do the exact same read and writes over SPI, but the older application reads all 0xFF values after soft reboot procedure (subsequent reads are not included in the following traces for simplicity purposes). I copy and paste corresponding portion of debug dump here for comparison purposes.

The question is what would lead to such difference? Do timing of SPI commands matter? note soft reboot is implemented exact same way in the deca device library with the necessary sleep to let clk PLL lock after reset.

SIMPLE_TX + MCP2210

Read 00 Data 30 01 ca de
Read 36 Data 00 02
Write b6 Data 01
Write f6 01 Data 02
Write f6 04 Data 00 00
Write ac Data 00 00
Write ec 06 Data 00
Write ec 02 Data 00
Write ec 02 Data 02
Write f6 03 Data 00
Write f6 03 Data f0
Read 36 Data 00 02

PREVIOUS APPLICATION

Read 00 Len 4 Data 30 01 ca de
Read 36 Len 2 Data 00 02
Write 36 Len 1 Cmd b6 Data 01
Write 36 01 Len 1 Cmd f601 Data 02
Write 36 04 Len 2 Cmd f604 Data 00 00
Write 2c Len 2 Cmd ac Data 00 00
Write 2c 06 Len 1 Cmd ec06 Data 00
Write 2c 02 Len 1 Cmd ec02 Data 00
Write 2c 02 Len 1 Cmd ec02 Data 02
Write 36 03 Len 1 Cmd f603 Data 00
Write 36 03 Len 1 Cmd f603 Data f0
Read 36 Len 2 Data ff ff

[amal.ka]

sir, can you please tell me is -5dB antenna is enough for 50M communication using dw1000 on channel 5 ? and how to calculate the link budget?