DW1000 IC PCB Schematic Layout - VDDPA1 & VDDPA2


I am trying to determine how the optimal layout of the VDDPA1 and VDDPA2 line should look like. I looked at different schematics provided by decawave. However, after looking at the schematics some questions came to my mind. First, lets look at the schematic recommended by the official DW1000 data sheet:

DW1000 data sheet pin numbering:


DW1000 data sheet decoupling circuit of VDDPA1 consists of:

47uF - 0.1uF - 10pF - 330pF

DW1000 data sheet decoupling circuit of VDDPA2 consists of:

0.1uF - 10pF - 330pF

So far so good, now lets look at the EVB1000 schematic:

In the EVB1000 schematic shown above VDDPA1 and VDDPA2 have switched pin numbering compared to the data sheet, which I assume is just a small mistake:

EVB1000 pin numbering:


In addtion, the decoupling circuits have changed slightly:

EVB1000 decoupling circuit of VDDPA1 consists of:

0.1uF - 10pF - 330pF

EVB1000 decoupling circuit of VDDPA2 consists of:

0.1uF - 10pF - 330pF

What happended to the 47uF capacitor for VDDPA1 ? I see that there is still a 47uF capictor in the schematc, but does this mean that this capcitor does not belong to the VDDPA1 decoupling circuit ?

Next, lets look at the DWM1001 schematic:

Like in the EVB1000 schematic pin numbering has switch compared to the official DW1000 data sheet:

DWM1001 pin numbering:


However, what interests me more is the change in the decoupling circuits:

Ferrite beads have been added, which is benifical for removing noise as discussed before in this forum. No need to discuss this further.

On top of that the capacitors have changed:

DWM1001 decoupling circuit of VDDPA1 consists of:

47uF - FB (ferrite bead) - 0.1uF - 330pF - 12pF

DWM1001 decoupling circuit of VDDPA2 consists of:

FB (ferrite bead) - 22uF - 0.1uF - 330pF - 12pF

In comparison to the DW1000 data sheet the follwing changes have been made:

  • for both pins ferrite beads have been added
  • for both pins 10pF has been increased to 12 pF
  • for VDDPA2 a capcitor 22uF has been added
  • for VDDPA1 the 47uF capacitor has been placed in front of the FB

Is this now considered to be the better refrence design ?

Lastly, lets look at the DWM1004 schematic:

Pin numbering is in accordance with the official DW100 data sheet:


More importantly, the decoupling cirucits now look like this:

DWM1004 decoupling circuit of VDDPA1 consists of:

FB (ferrite bead) - 47uF - 0.1uF - 330pF - 10pF

DWM1004 decoupling circuit of VDDPA2 consists of:

FB (ferrite bead) - 0.1uF - 330pF - 10pF

In comparision with the schematic DWM1001 schematic there are the follwing differences:

  • for both the 12pF capacitors have been decreased to 10pF
  • for VDDPA2 the 22uF capacitor has been removed
  • for VDDPA1 the 47uF capacitor is placed after the ferrite bead

This leads to the question if this design is considered to be superior ?

Lets assume for a moment the schematics of the data sheet and the evb1000 are outdated.

Then there is the following choice:

OPTION 1 - DWM1001:

DWM1001 decoupling circuit of VDDPA1 consists of:
47uF - FB (ferrite bead) - 0.1uF - 330pF - 12pF

DWM1001 decoupling circuit of VDDPA2 consists of:
FB (ferrite bead) - 22uF - 0.1uF - 330pF - 12pF

OPTION 2 - DWM1004:

DWM1004 decoupling circuit of VDDPA1 consists of:
FB (ferrite bead) - 47uF - 0.1uF - 330pF - 10pF

DWM1004 decoupling circuit of VDDPA2 consists of:
FB (ferrite bead) - 0.1uF - 330pF - 10pF

Or could it also be this, which is not mentioned anywhere:

OPTION 3 - Not removing the 22uF capacitor with 10pF:

Decoupling circuit of VDDPA1 consists of:
FB (ferrite bead) - 47uF - 0.1uF - 330pF - 12pF

Decoupling circuit of VDDPA2 consists of:
FB (ferrite bead) - 22uF - 0.1uF - 330pF - 12pF

OPTION 4 - Not removing the 22uF capacitor with 12pF:

It would be great if a decawave person could clear things up regarding this matter.

What has been proven to be the best arrangement of these circuits ?

I would be also very happy if someone could share how he or she solved this layout question.

To sum up:

Where to place the 47uF capacitor for VDDPA1 ?
Before or after the ferrite bead ?
Or should it not be included at all ?

Where to place the 22uF capacitor for VDDPA2?
Or should it not be included at all ?

What size should the smallest capacitors have ?
10pF or 12 pF ?

Looking forward to your help.

Best regards,

Not a decawave person but my 2 pence / cents / monetary unit of choice:

The 47 uF is mainly there as a bulk capacitance close to the pins, whether it’s on VDDPA1 or VDDPA2 doesn’t make much difference if you don’t have the ferrites, if it’s close to one it’s close to the other.

Putting ferrites in line with the power input on a chip is very dependent on the situation.
Pros: Forces separation of the power feeds into each pin and so enforces good layout. Helps if your power supply has noise. Helps if the layout could result in noise coupling between power pins.
Cons: Requires you to fit more parts into a crowded part of the layout where you are trying to minimize track lengths. If you put insufficient capacitance after the ferrites then your design won’t work.

So if you don’t use ferrites I’d say a 47uF at the point where you connect to the plane and then two separate lines of 0.1uF, 330pF and 10pF (in that order) from that point to each VDDPA pin keeping everything as short as possible. We ended up putting those parts at an odd angle to fit them in tighter and still get the RF feed out.

If you were to use the ferrite approach then personally I’d go with option 5: 47uF at a common point before the ferrites and 22uF on both of the feeds after them.

Given the tolerances of the parts and the variation caused by things like pad sizes etc… I don’t think 10 or 12 pF will make much difference. At 4 GHz you’ll get more difference going from 0402 to 0603 than you would going from 10 pF to 12 pF. And that sort of thing is easy to change after the board is made so you can try both and see if there is any difference in performance.

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Even though I’m a Decawave person, I wasn’t involved in the design of the modules or the DW1000. I will try to discuss this with someone who knows a bit more.

The “best” arrangement of decoupling components depends on the use and how you think about it. You could consider the decoupling caps and the FB having 3 main functions:

  1. Preventing voltage drops at the pin and thus ensuring the PA always has sufficient current for a correct operation
  2. Preventing transient currents from propagating to the power supply, important to keep the supply regulators stable
  3. Preventing radio signals from propagating on the supply line, preventing unintended radiated emissions from the supply rails.

Optimizing for point 1 means FB -> 47uF cap -> smaller caps -> pin like option 3-4 will work best since the big decoupling cap will allow the pin to draw big transient currents without being choked by the FB.
For point 2 and 3 the 47uF cap -> FB -> smaller caps -> pin would work better since the FB will typically be better at blocking the high frequency noise / transients, effectively forming a pi filter.

To be honest. looking at the datasheet of the FB used, I don’t think the filtering of the modules is optimal, since it is designed to block EMI noise at 100-1000MHz.

The DW1000 IC supports UWB channels 1-5 and 7, ergo a frequency of 3244.8-6998.9 MHz. At these frequencies the FBs won’t block a lot. It could be though that the designer is filtering lower frequency noise I’m not aware of. Either way, all modules passed EMI verification, so the EMI is blocked sufficiently to meet regulations.

The optimal decoupling cap values depend on the used frequency, and thus on the used UWB band. Note that the DW1004 was mainly designed for TDoA applications, requiring mainly TX operation from the tags. This could explain the difference in decoupling caps, but as Andy mentioned, the effect will be minimal. It could also be the 12pF caps where found to work better empirically, but I was not able to find anything on this.

TL;DR: the module designs pass EMI regulations (at least in band 2 and 5 as far as I am aware) and work as intended, your mileage may vary since a lot depends on the PCB layout, size and even stackup and component sizes, as well as the used bands, but if you follow the suggestions in the datasheet you should be fine.



first of all thank your for your answers @AndyA @seppe.

so basically I have the choice between the layout recommended by the data sheet:


and the option proposed by you @AndyA:


does anyone have an idea why decawave made their circuit asymmetric in the DWM1003 layout regarding the 22uF capacitor ?


what do you guys think is the safest way to go ?

and another question regarding capacitor placement:

the DWM1000 places the 47uF capacitor next to the balun.

however the DWM1003 places the 47uF capictor on the opposite side of the chip in order to fit the 22uF capacitor close to the VDDAP pins. do you have any suggestions what the optimal placement strategy is regarding these capacitors ?

kind regards,

Whether the difference between option Andy and option DWM1003 is important will come down to the exact nature of the current variation on the VDDPA1 pin. Personally I’m paranoid on this sort of thing, I’ve seen power systems like this give unreliable and poor behavior due to lack of capacitance after the ferrite. I’ve never seen systems fail due to too much capacitance there. So I tend towards more rather than less as a precaution.

On our board we didn’t have the ferrites and ended up with the schematic as per the datasheet option with the layout shown below. This seems to be working fine for us so far.

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I discussed this internally, my short answer for now is: it’s complicated, and we plan to document this better.

In general it seems like I was wrong about the ferrite beads in my previous comment. The ferrite beads are primarily used to isolate noise between VDDPA1 and VDDPA2. This mainly has effect on the bandwidth of the transmitted signal, and thus on the performance. I should not not impact EMI to much (it should be OK for certification).

I’m a fairly new hire, so I have more spare time to answer forum posts, but sadly I don’t have that much background. Sadly the person that would know most about this is currently not in the office and is busy with new designs, so I started an internal mail thread about this. It could take some time to have a proper answer. I (or someone that knows more) will provide an update you once we have more information and hopefully we can improve our documentation on this in the future.

For now I would suggest the “ANDY” option. The 22uF are not strictly needed as far as I understand, but as @AndyA mentioned having more capacitors is typically a better option than having too little. The 22uF caps can always be left unconnected. Just make sure to avoid stubs. See also section 6.2 and 6.3 in the hardware design guide (APH001) and section of the DW1000 user manual:

It should be noted that if you plan to use DA setting 000 you must ensure good isolation between pins VDDPA1 and VDDPA2 otherwise this setting may result in compression of the TX signal. ( Good isolation requirIate PCB tracks to each of these pins. )

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Hi Firstdragon,

Apologies for the confusion. As Seppe states, each of our module reference designs have passed the regulatory tests so you can’t go wrong following either DWM1001/3 or DWM1004. The DWM1001 design originated outside of Decawave and there were some small variations in component values that we decided not to change.

I’d suggest copying what we’ve done on DWM1004, which is the same as the DW1000 datasheet application circuit but with the ferrites added, which introduce isolation between the VDDPA pins and prevent the output stages compressing at high transmit gain settings.

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I greatly appreciate your effort and I am already looking forward to the result of the discussion on this matter since this is a important topic regarding DW1000 PCB layout.


thank you for your reply.

your recommendation is to consider the DWM1004 layout as reference layout which is shown on the picture below:

this would translate to the following schematic:

this raises the question why the two lines are treated in different manner ?

why does the VDDPA2 line need a different layout than the VDDAPA1 line ?

in addtion also the issue of insufficient capacitance after the ferrite beads brought up by @AndyA is worth to be considered if VDDPA2 line has no capacitance after the ferrite beads like in the DWM1004 design.

it is my intention to get the maximum performance out of DW1000 and not to make the design “just work”. therefore every bit of information or any advice in order to achieve this goal is greatly appreciated.

kind regards

Hey Firstdragon

I asked Stephen (@S_Carroll_DW) the same question and his response is:

I believe VDDPA1 has a higher current draw compared to VDDPA2. The reason we have the 47 uF btw is to prevent pulling of the internal 38.4 MHz oscillator circuit.

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Hi Firstdragon,

Although in theory it shouldn’t do any harm, I just don’t quite see the logic in adding another 22 uF on the VDDPA2 trace. If you’re trying to enhance the filtering effect of the ferrite, you’ve already got the 100 nF cap, which is plenty. In fact, in practice, adding that extra 22 uF cap could well compromise the design by complicating what’s already a really congested area to route.

I’ve evaluated enough DW1000 designs to be confident that DWM1004 achieves maximum performance. By all means try out whatever decoupling ideas you have and let us know if you think you get more.


I think it is based on the DWM1001 design, where a 22uF cap is connected between the ferrite and the VDDPA1 pin (incorrectly labeled VDDPA2).

Since we don’t explain the difference between the 2 VDDPA pins it doesn’t make a lot of sense the decoupling would be different. This together with the incorrect pin labeling and the fact that the 47uF cap is connected to the ferrite after the VDDPA2 (incorrectly labeled VDDPA1) in the schematic causes some confusion.

If I understand correctly, both pins are used to power different stages in the TX amplification, but this is not super clear and the naming could suggest the pins have the same function.

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@seppe thank you. now the hardware design guidelines and example schematics make much more sense to me. :+1: