I am having troubles changing the mode of a DW1000 from RX to TX.
What I am doing is the following:
- After I am done with RX, I set Bit 6 (TRXOFF) in SYS_CTRL register and wait until it is cleared:
def disableTransceiver(self):
SYS_CTRL = self.read(reg_addr=0x0D, sub_reg_addr=0x00, len=4)
SYS_CTRL[0] |= (1 << 6)
self.write(reg_addr=0x0D, sub_reg_addr=0x00, data=SYS_CTRL)
while True:
SYS_CTRL = self.read(reg_addr=0x0D, sub_reg_addr=0x00, len=4)
TRXOFF = SYS_CTRL[0] & (1 << 6)
if TRXOFF == 0:
break
- I write TX-Data into the buffer and set TX buffer length:
def writeTXData(self, data):
self.write(reg_addr=0x09, sub_reg_addr=0x00, data=data)
data_len = len(data) + 2
tx_fctrl = self.read(reg_addr=0x08, sub_reg_addr=0x00, len=5)
tx_fctrl[0] = data_len & 0xFF # set 7 bit data length
tx_fctrl[1] |= (data_len >> 8) & 0x03
tx_fctrl[1] |= (1 << 6) # set transmit bit rate 6.8Mbps
self.write(reg_addr=0x08, sub_reg_addr=0x00, data=tx_fctrl)
- I start transmit and wait until TXFRS bit in SYS_STATUS reg is set:
def sendTX(self):
sys_ctrl = self.read(reg_addr=0x0D, sub_reg_addr=0x00, len=4)
sys_ctrl[0] &= ~0x01 # Disable Suppress auto-FCS
sys_ctrl[0] |= (1 << 1) # Transmit Start
self.write(reg_addr=0x0D, sub_reg_addr=0x00, data=sys_ctrl)
while True:
SYS_STATUS = self.read(reg_addr=0x0F, sub_reg_addr=0x00, len=5)
TXFRB = SYS_STATUS[0] & (1 << 4)
TXPRS = SYS_STATUS[0] & (1 << 5)
TXPHS = SYS_STATUS[0] & (1 << 6)
TXFRS = SYS_STATUS[0] & (1 << 7)
TXBERR = SYS_STATUS[3] & (1 << 4)
CLKPLL_LL = SYS_STATUS[3] & (1 << 1)
if TXFRB != 0:
print("Transmit Frame Begins.")
if TXPRS != 0:
print("Transmit Preamble Sent")
if TXPHS != 0:
print("Transmit PHY Header Sent")
if TXFRS != 0:
break
if TXBERR != 0:
print("Transmit Buffer Error")
if CLKPLL_LL != 0:
print("Clock PLL Losing Lock")
Unfortunately, neither TXFRB, TXPRS, TXPHS nor TXFRS get set ever. Do you know what this could be?