DW1000 can't receive at all due to CLKPLL_LL being set constantly

I have one DW1000 module which I program the exact same way as my other DW1000 module, however, it can only transmit but never receive because the CLKPLL_LL bit is set, even if I set TRXOFF:

def waitForSuccessfulReceive(self):
    start_time = time.time()
    self.activateReceiver()
    while True:
        SYS_STATUS = self.read(reg_addr=0x0F, sub_reg_addr=0x00, len=5)

        RXFCG = SYS_STATUS[1] & (1 << 6)
        RXDFR = SYS_STATUS[1] & (1 << 5)

        LDEERR = SYS_STATUS[2] & (1 << 2)
        RXFCE = SYS_STATUS[1] & (1 << 7)
        RXPHE = SYS_STATUS[1] & (1 << 4)
        RXRFSL = SYS_STATUS[2] & 0x01

        RXRFTO = SYS_STATUS[2] & (1 << 1)
        RXPTO = SYS_STATUS[2] & (1 << 5)
        RXSFDTO = SYS_STATUS[3] & (1 << 2)

        LDEDONE = SYS_STATUS[1] & (1 << 2)

        RFPLL_LL = SYS_STATUS[3] & 0x01
        CLKPLL_LL = SYS_STATUS[3] & (1 << 1)

        if RXFCG != 0 and RXDFR != 0 and LDEDONE != 0:
            break
        if time.time() - start_time > 1.0:
            break
        elif RFPLL_LL != 0:
            print("RF PLL Losing Lock")
        elif CLKPLL_LL != 0:
            print("Clock PLL Losing Lock")
            self.disableTransceiver()
            time.sleep(0.01)
            self.activateReceiver()
        elif LDEERR != 0:
            print("Leading edge detection processing error")
            self.activateReceiver()
        elif RXFCE != 0:
            print("Receiver CRC error")
            self.activateReceiver()
        elif RXPHE != 0:
            print("Receiver PHY Header error")
            self.activateReceiver()
        elif RXRFSL != 0:
            print("Receiver Reed Solomon Frame Sync Loss")
            self.activateReceiver()
        elif RXRFTO != 0:
            print("Receive Frame Wait timeout")
            self.activateReceiver()
        elif RXPTO != 0:
            print("Preamble detection timeout")
            self.activateReceiver()
        elif RXSFDTO != 0:
            print("Receive SFD timeout")
            self.activateReceiver()

Is my module broken - what is causing this?

Can someone help me please? I have the same problem with two other modules and I don’t know what to do

Hi @maxG
the datasheet says it clearly - the PLL is having a locking issues. This seems to be related to some HW issues. Could you post schematics and PDB Gerber files - I can take a look at it if you want.

In general I could be a bad wiring around Xtal, some noise around PLL parts or noisy power line.

Cheers
JK

1 Like

Hi,

I use this board:

and I basically just connected SPI, GND and VCC to a Raspberry Pi 4 (using loose wires) with a single 220nf capacitor between GND and VCC.

Do you know why this seems to happen predominantly in RX-mode?

Hi @maxG
the RX mode needs much more power. What I would expect here is that the RPi4 generates too noise into the 3V3 that it corrupts the DW3K chip.

How do you power the RPi4?

Cheers
JK

Replace that 220nF with something more like 10uF. The module already contains smaller high frequency capacitors. But if you are connecting power over wires from source that could be being pushed towards it’s upper output limit then a large local capacitor right on the modules power pins could make a difference.

Hi JK,

I use a 15W power supply which powers the RPi via USB-C.
Up to this point I still could not resolve the issue.