Drift of internal chips clocks


we are trying to synchronize two DW1000 chips which share accurate 38.4MHz reference clock with SYNC pin.

Are there any, published or not, application notes, articles where accuracy of internal clock generators and PLLs is provided?
Our goal is to synchronize two chips on the same board as rarely as possible but at the same time keep timestamp counters coherent as much as possible, as long as possible.
Currently, measured drift between two DW modules is extremely linear and we presume that main source of it is from on board oscillator but we would like to confirm it.