Hi,
I just tried testing Dflop in both SPICEs, and see the response to PRE and CLR are different. Please see the waveform below. Any comments why is that?
Thanks!
Yi
A long time ago on the LTspce forum it was discovered that the CD4013 model is somewhat defective. This was also discussed on the Russian forum. As a rule, this is not noticeable. Perhaps Qspice decided to fix this.
Here is the CD4013 schematic:
Hi Bordoynov,
Have checked the function table of CD4013B. See below:
Looks like when SET=RESET=1, both Q and _Q are 1, which is the same as LTSPICE’s result…
And what happens when you change SET and RESET to low at the same time ?
Is there right and wrong if both SET and RESET equals 1 for D-type flip-flop?
SET (PRE) represent to force Output Q to 1
RESET (CLR) represent to force Output Q to 0
Setting both SET and RESET to 1 is defined as Illegal concurrent, some will call it forbidden state.
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I change SET and RESET to go up and down at the same time:
When RESET and SET are both 0, the output follows CLK edge.
Kelvin, you are right. Just wondering why LTSPICE and QSPICE gives different results when both are high. They are both developed by Mike…
I think you can contact Mike to review if it worth a change if you truly have a need for Q to be 1 when both RESET and SET are high and for this logic to match CD4013.
Qspice does not include the LTspice A-device, which is Analog Device IP. This could be why the logic devices in Qspice do not follow A-device logic.
However, since RESET=SET=1 is typically considered not to be used, and different simulators implement their responses differently, it’s uncertain if anything needs to be done about that. Alternatively, you can actually use C++ to write a D flip-flop that provides such a response. There are no limitations on how logic is implemented with the support of a C++ block.
You should consider Qspice as something entirely new. For example, something in LTspice that is regarded as good but not implemented in Qspice may be seen as bad (e.g., L in capacitor model, modified Trap integration).
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See 74HC74:
This is an example to use C++ block to implement a D-flop with CD4013B logic table. I hope I didn’t make a mistake here.
D-flop-CD4013B.qsym (904 Bytes)
d_flop_cd4013b.cpp (3.4 KB)
D-FLOP-CD4013B - Truth Table.qsch (6.7 KB)
Hi Kelvin,
Really appreciate your effort and explanation up there.
The logic in the C++ file looks right to me.
Thanks, the logic looks the same to CD4013 and the footnote is clear.