Hi,
I use DW1000 with a custom firmware on Contiki OS. Last week I have try to put the DW1000 in deep sleep to save energy. Sometimes, the DW1000 wakeup just after being put in deep sleep.
In detail here is the code I used to put the DW1000 in deep sleep:
[code]/* Configure the Always ON system control /
uint16_t aon_wcfg = 0; / AON Wake-up Configuration /
uint8_t aon_ctrl = 0; / AON Control /
uint8_t aon_cfg0 = 0; / AON Configuration Register 0 /
uint8_t aon_cfg1 = 0; / AON Configuration Register 1 */
/* According to DECADRIVER "The 3 bits in AON CFG1 register must be
cleared to ensure proper operation of the DW1000 in DEEPSLEEP mode. */
dw_write_subreg(DW_REG_AON, DW_SUBREG_AON_CFG1, 1,
&aon_cfg1);
/* Reset AON Control value*/
dw_write_subreg(DW_REG_AON, DW_SUBREG_AON_CTRL, DW_SUBLEN_AON_CTRL,
&aon_ctrl);
/* On wake-up run the temperature and voltage ADC /
aon_wcfg |= DW_ONW_RADC_MASK;
/ On wake-up upload the configuration from the AON memory /
aon_wcfg |= DW_ONW_LDC_MASK;
/ On wake-up load the LDE code
(useful for correct timestamps and RSSI value) */
aon_wcfg |= DW_ONW_LLDE_MASK;
/* On wake-up load the LDO tune value */
if(dw_is_ldotune()){
aon_wcfg |= DW_ONW_LLDO_MASK;
}
/* Sleep enable configuration bit. In order to put the DW1000 into the
SLEEP state this bit needs to be set and then the configuration needs
to be uploaded to the AON using the UPL_CFG bit in AON_CTRL */
aon_cfg0 |= DW_SLEEP_EN_MASK;
/* Enable Wake up using SPI CSn or WAKE UP pin. */
aon_cfg0 |= DW_WAKE_PIN_MASK;
// aon_cfg0 |= DW_WAKE_SPI_MASK;
/* Enable interrupt flag for the clock PLL lock event and
SLEEP to INIT event */
dw_clear_pending_interrupt(DW_MCPLOCK_MASK|DW_MSLP2INIT_MASK);
dw_enable_interrupt(DW_MCPLOCK_MASK|DW_MSLP2INIT_MASK);
dw_write_subreg(DW_REG_AON, DW_SUBREG_AON_WCFG, DW_SUBLEN_AON_WCFG,
(uint8_t *) &aon_wcfg);
dw_write_subreg(DW_REG_AON, DW_SUBREG_AON_CFG0, 1,
&aon_cfg0);
/* Upload the AON block configurations to the AON and then enter in sleep
because SLEEP_EN is set./
aon_ctrl = DW_SAVE_MASK;
dw_write_subreg(DW_REG_AON, DW_SUBREG_AON_CTRL, DW_SUBLEN_AON_CTRL,
&aon_ctrl);
aon_ctrl = DW_UPL_CFG_MASK;
dw_write_subreg(DW_REG_AON, DW_SUBREG_AON_CTRL, DW_SUBLEN_AON_CTRL,
&aon_ctrl);
/ then I disbale the PULL up resistance and I set in input the pin SPI CLK, MISO and GPIO */
[/code]
In resume:
- I clear the AON_CFG1 register (needed according to your driver).
- I reset the AON_CTRL register.
- I enable interrupt of the GPIO pin in case of clock PLL lock event or SLEEP to INIT event (the second case not append because I set the ONW_LLDE bit later).
- Then I configure the AON_WCFG register:
- On wake-up run the temperature and voltage ADC
- On wake-up upload the configuration from the AON memory
- On wake-up load the LDE code
- On wake-up load the LDO tune value
- I configure the AON_CFG0 register to enable the sleep mode and to wake up on the WAKEUP pin.
- Then I put the dw1000 in sleep (here your driver does not follow the user manual indication then a made my best).
First I write the SAVE bit to the AON_CTRL register (to save the DW1000 state in the AON memory) then I write the UPL_CFG bit to put the DW1000 in sleep.
If I wakeup on the SPI CSn then sometimes the node wakeup itself 2.6 ms after being put in deep sleep, but if I use the Wake up (WAKE_PIN set in AON_CFG0 but not WAKE_SPI) then the deep sleep work as expected.
I check the DW1000 state using a logical analyzer connected to the SPI (CLK, MISO, MOSI, CSN), GPIO and RSTn pin.
When I put the DW1000 in sleep, the SPI.MISO pin state HIGH for 1.9ms after the end of the last SPI transaction (SPI CSN low).
I also observe the SPI.CSn pin drive low for 20µs just 618 µs after the end of the last SPI transaction (I suppose this event as the wakeup trigger) but in my driver I don’t drive the SPI.CSn low at this time.
My question is the following: first, why in your driver you put the DW1000 in sleep using only the SAVE bit of the AON_CTRL register when the manual indicated to use the UPL_CFG bit.
Second, do you observe the same not expected wakeup on your platform?
Finally, it is possible for the DWM1000 to drive the SPI.MOSI (the spi master pin) high and the CSn LOW it shelf ?
I can send you the logical analyzer trace (I use a Saleae model, it’s open source) if you want.
Thanks in advance,
Maximilien