Could I please get the Coff capacity of the components QPC2420/QPC0542/QPC2320?

RF Solutions RF All Other (switches, controls, attenuators, ..)
1

Could I please get the Coff capacity of the components QPC2420/QPC0542/QPC2320?

2

The off capacitance (Coff) for these switches is not specified. Why do you need to know the Coff? Is this in relation to isolation, or some other parameter? Note that these switches are series-shunt configuration, so it’s not just the Coff but the Ron that defines performance. The QPC0542 s-parameters can be used to analyze performance.

3

Ich möchte den Reflexiongrad bei einem offenen pin umschaltkontakt berechnen, ich möchte eine leistungsberechnung nachbilden. Deshalb wäre die Coff Kapazität für mich wichtig. Grüße

4

Thanks. I understand that you can calculate the Coff from s-parameters. I haven’t tried it myself. There is some literature available online on how to do this. Not sure exactly on your question, relating to the switch changeover? There is a specification in the datasheet for maximum power for ‘hot switching’. This is when RF power is present when the switch path is changed from RF1 to RF2. You need to de-rate input power by 4dB when ‘hot switching’.

5

Here is a description of my use case, which I intend to implement using
the QPC2320, QPC2420, and QPC0542 components.

I want to simulate a physical line break that must be possible from 1 µs
to permanent.
Both ultra-short and permanent breaks are possible.
Overshoot should also occur when the line suddenly becomes high-impedance.

I would like to use the Qorvo SPDT Reflective Switch.
Depending on the type, the signal has a bandwidth of 1 MHz to 12 MHz but
low power levels of < 4 dBm.

Switch requirements:

  • RFC to RF1 closed → high isolation to RF2, low insertion loss
  • RFC to RF2 closed → high isolation to RF1, low capacitance on RF1,
    maximum reflection on RF1 and RFC to RF2

In the layout, I would leave the RF2 pin unconnected and the pad to GND
omitted to minimize capacitance to GND.

Could you please confirm that maximum reflection occurs in the switch
when RFC to RF2 is closed?

6

Thanks. Not sure exactly what you mean with the last question:
‘Could you please confirm that maximum reflection occurs in the switch when RFC to RF2 is closed?’
When RFC is connected to RF2 then the RF1 port will reflect power, as the shunt FET on RF1 will be turned on and the series FET connected to RFC will be open. Note that on RF1 and RF2 ports there are shunt FETs, so when the port is not selected the shunt FET will be turned on making them near a short circuit to ground.

7

Thank you for your support.

I have revised the description based on your additional information and hope that all requirements are now addressed:

State: RFC to RF1 closed (Active Path)

  • RFC to RF1 Connection: Minimum insertion loss.
  • Isolation: High isolation from RFC and RF1 to RF2.
  • RF2 Path (Open): The shunt FET is enabled, creating a short circuit to ground (GND).

State: RFC to RF2 closed (Active Path)

  • Isolation: High isolation towards RF1.
  • RF2 Characteristics: RF2 should feature a very low off-state capacitance.

Layout Optimization: To minimize parasitic capacitance to ground, the RF2 pin will remain unconnected in the layout, and the pad will be cleared (voided) from the ground plane.

Objective: Achieve maximum reflection at RF2 and, consequently, at RFC.

  • RF1 Path (Open): The shunt FET is enabled, creating a short circuit to ground (GND).

Objective: Achieve maximum reflection at RF1.