Combine QSPICE Netlist and Verilog DLLs into a Symbol

[KSKelvin]

@KSKelvin

In your case, as you have multiple .subckt within this hierarchical block, make sure you select the option “Include Entire File” from autogenerate symbol. Or, some .ends line may be discarded in this process and return Fatal error in your generated symbol.

Update to latest Qspice and this is no longer an necessary action
08/16/2025 Fixed a problem importing subcircuits that next subcircuits.

Here is a complete procedure