Combine QSPICE Netlist and Verilog DLLs into a Symbol

[KSKelvin]

I assume you know the standard autogenerate a symbol process from a hierarchical block.
In your case, as you have multiple .subckt within this hierarchical block, make sure you select the option “Include Entire File” from autogenerate symbol. Or, some .ends line may be discarded in this process and return Fatal error in your generated symbol.
After this symbol is generated, this symbol file and .dll file must be share together. The .dll file have to be in same folder of the schematic that simulate, or it directory is added into Symbol & IP browser in Qspice.