Clock Drift Compensation for ranging

Yes, indeed that seems to be the case. Therefore I used an exponentially weighted moving average of the CRI value to reduce its noise.
However, there is a dependency between the response delay and the precision and accuracy of the ranging. If your delay is sufficiently low a uncorrected ranging will perform better than a corrected one. However, for larger delays or for a high clock speed offset you will need a correction method.

PS: I’ve written my thesis about this topic and have done some further measurements. If you are interested I can send you a copy.

Yes, I am highly interested in your thesis. Please send me a copy.
Thank You.

Hello, mschuh, can you also send me a copy of your thesis?
Thanks a lot.

Hey,
What PPM do you use for crystal oscillator?

The used crystal had a 10ppm accuracy. However, you can use the crystal trim feature (register: FS_XTALT) of the DW1000 to perform a calibration. Thereby you may reduce the clock speed offset below ~0.8ppm. The rest may be corrected via the CRI or RTT values.

May you share your thesis to me? I’m a student of Wuhan university, and my research is about UWB?and my email is zyliu0017@whu.edu.cn. ths…

Hi,

Please let me know the Carrier Recovery integrator (Cint) in the following equation is in decimal?
F_offset=(Cint*2^(-17))/2(N_sample/Fs)
why 2^(-17) is used in the above equation?

Best Regards

See UM , 7.2.40.11 Sub-Register 0x27:28 – DRX_CAR_INT

This information is available in the carrier recovery integrator register, at address 0x27, offset 0x28. This is a 21 bit number with the lower 17 bits, the fractional part, and the upper 4 bits as the integer portion of the number.
Leo

Thank you. I mean, I should convert Cint to decimal and insert it into the F_offset equation?
I have used two DW1000, one as a transmitter and other one as a receiver. The transmitter has sent 28 packet and receiver has estimated frequency offset as follows:
[0.0667 0.0673 0.0649 0.0778 0.0754 0.0608 0.0796 0.0652 0.0767 0.0613 0.0795 0.0860 0.0791 0.0737 0.0573 59.4889 0.0729 0.0771 0.0999 0.0933 0.0797 0.0779 0.0963 0.0843 0.0774 0.0930 0.0875 0.0816]
are theses frequency offsets correct? I know the maximum value of frequency offset can be about 59 Hz. why the 15th F_offset is 0.0573 then 16th F_offset is 59.4889?

Hi,

I’m not sure how you get these figures or what procure you follow. For trimming we have example code sending continues waves to trim the crystal, example 4a.
for the TRIM procedure itself see IC user manual section 8.1.

leo

Thank you. where can I find the example 4.a?

What examples and where to find them has been reported a few times.
See: USe of example code

Regards
leo

The link does not work [https://decawave.com/support/software ]

https://www.decawave.com/software/

Hello,mschuh,can you also send me of your thesis,my email is zhangyongshun@aliyun.com. Thanks a lot.

Hello @mschuh, I forgot to attach my email address last time. Could you please send me a copy of your paper?

jianing_zhang2021@163.com

Moreover, the clock drift I calculated using CRI looks a little strange compared with @FIRSTDRAGON

1

initiator side

2

Response side after no interval switchover
( The X-axis is the number of samples, and the Y-axis is in PPM)

What was the temperature doing at the time?
It looks like you started logging at power up which is why there is a rapid change initially.
If this is a circuit sitting out on a desk then changes in airflow in the room could impact it. Put everything inside an insulated box or some other method to isolate it from external influences and let it run for a while before you start logging and you’ll probably get a far more stable trace.

If you have anti-static bubble wrap around then putting some of that around the board is a simple way to buffer it from changes in the room. Don’t use normal bubble wrap.

[mschuh] I also struggle about this topic. May I get a copy of your thesis?

Thank you.

You are right.