CLKPLL_LL status bit on DW1000

Hi to all

I’m trying to move the evk1000 demo application on a different microcontroller, it don’t work and i notice that the CLKPLL_LL bit, in the status register, is set just after the power on, I send just the devid command that work fine and then read the status byte.

Can be an hardware problem on my module?

By the way is the demo application on EVK1000 evaluation kit work only if anchor0 is in range. Is this a limitation of the demo or the anchor 0 have to be always on and in range in any case?

Thank you in advance


The DW1000 includes a phase locked loop (PLL) to providing the clock signal to the digital circuitry (CLKPLL).
Once enabled / configured correctly, this PLL should lock to its target frequency and remain locked.
There is a CLKPLL Loss-of-Lock event bit (CLKPLL_LL) in the System Status Register at address 0x0F. When set, this bit indicates that the CLKPLL has lost lock. Some customers have reported observing this bit being set under various conditions.
The DW1000 user manual states: “This event status bit is set to indicate that the system’s digital clock PLL is having locking issues. This should not happen in healthy devices operating in their normal range.”
If you observe this bit as being set, you should first of all check that the PLLLDT bit in Register file 0x24:00 –EC_CTRL is set. This is required to ensure reliable operation of this CLKPLL_LL bit. See also the note in the CLKPLL_LL register description in IC user manual.
Assuming the PLLLDT bit is set and you still observe that the CLKPLL_LL bit is set then there are a number of potential causes: -

(1) The CLKPLL has not yet locked and SPI read operations from the DW1000 are being attempted at too high an SPI clock rate.
The SPI interface to the DW1000 uses the on-chip system clock. When the CLKPLL is locked this system clock is provided by the CLKPLL and the maximum permitted SPI CLK is approx. 18 MHz; however, on start-up or reset, the CLLKPLL will not be locked and the system clock is provided by the crystal oscillator at a much lower frequency. In this mode of operation the maximum permitted frequency of the SPI CLK is in the region of 3 MHz. While in this mode, any attempted reads from the DW1000 at SPI CLK rates in excess of 3 MHz will return invalid data. You should allow sufficient time for the CLKPLL to lock before accessing the DW1000 at the higher SPI CLK rate.
In particular, when using Decawave’s API it is important that the dwt_initialise function uses the lower SPI CLK rate.

(2) While the DW1000 is not unduly sensitive to power supply noise, any significant noise on the VDDCLK or the primary 3V3 supply could cause potential problems. It is important to decouple supplies properly and to follow the guidelines presented in the DW1000 data sheet and Decawave’s hardware design guide APH001.

(3) A faulty component or a manufacturing issue on the PCB. The CLKPLL uses off-chip loop filter components – see the circuit connected to the CLKTUNE pin (pin 8) in the application circuit in the DW1000 data sheet. A manufacturing issue (soldering for example), an incorrect value component or a fault in any of these components can result in the CLKPLL failing to lock.

(4) If you have investigated all the potential causes outlined above without finding any problem then the fault may lie with the DW1000 itself and you should consider replacing the part.

Hi leo

Thank you for your help

I check PLLLDT bit in Register file 0x24:00 –EC_CTRL and it is set, this is the register content 11011110101011010000000000000100 read with the command:

and this is the content of status register 10100000000000000000000010 read with the command.

My sequence is:
- Power on the module
- Wait some second
x=dwt_read32bitreg(EXT_SYNC_ID) ; // read status register low 32bits
x=dwt_read32bitreg(SYS_STATUS_ID) ; // read status register low 32bits

deviceid is read correctly
In the inittestapplication() i remove the SPI clock increase.
The initapplication() is the init routine of the EVK1000 demo kit application

I think that can be an hardware problem and i will try to replace the module as soon as i get a new one.

[color=#333333] the maximum permitted SPI CLK is approx. 18 MHz[/color]
[color=#333333]The datasheet says the maximum permitted SPI CLK is 20MHZ, Which one is correct?[/color]
[color=#333333]I use the SPI CLK 18 MHz in idle mode, but some boards have a CLKPLL Loss-of-Lock event occasionally. When I use the 14MHZ or 9MHZ SPI CLK, It’s not going to happen.[/color]

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