I am trying to reduce the gain of the CMD283C3 LNA MMIC to < 0 dB when transmitting. This has to be done rapidly (< 1us) to meet our transmit-receive timing requirements Per the datasheet, the drain voltage needs to be applied before gate voltage is applied and vice versa (gate voltage needs to be removed before drain voltage is removed). This gate voltage sequencing requirement more or less precludes drain switching (i.e. putting a P-MOSFET in series with the drain), which is a tried and true method of fast LNA blanking.
This leaves gate-switching. However, the descriptions of the gate and drain pins on page 8 of the data sheet indicate “decoupling and bypass caps required”. The application circuit on page 9 shows 100pf || 1000pf || 0.33uf on both the gate and drain pins. This is too much capacitance to switch rapidly through the recommended bias resistor (3k ohms).
Will this part remain stable with 100pf or less on the gate?