I am trying to reduce the gain of the CMD283C3 LNA MMIC to < 0 dB when transmitting. This has to be done rapidly (< 1us) to meet our transmit-receive timing requirements Per the datasheet, the drain voltage needs to be applied before gate voltage is applied and vice versa (gate voltage needs to be removed before drain voltage is removed). This gate voltage sequencing requirement more or less precludes drain switching (i.e. putting a P-MOSFET in series with the drain), which is a tried and true method of fast LNA blanking.
This leaves gate-switching. However, the descriptions of the gate and drain pins on page 8 of the data sheet indicate “decoupling and bypass caps required”. The application circuit on page 9 shows 100pf || 1000pf || 0.33uf on both the gate and drain pins. This is too much capacitance to switch rapidly through the recommended bias resistor (3k ohms).
Will this part remain stable with 100pf or less on the gate?
Hi Michael. I replied to you directly after you emailed appsupport@qorvo.com. I noted that this device can have the drain and gate biased at the same if needed among other recommendations.
Could you also share your recommendations, I have encountered the same problem. I am trying to turn the amplifier on and off by controlling Vgg using the GPIO chipset through a resistive divider of 1k and 1k ohms.
I determined that the chip was still stable with only 100pF bypassing the Vgg pin. I also had 2dB of attenuation at the RF output of the chip. With < 2dB RF output attenuation, there were some combinations of source and load impedance which caused the chip to oscillate. With 2dB attenuation, I couldn’t get the chip to oscillate for any combination of source and load impedance I tried, even when I cooled the chip down to -40C).
With 100pf bypassing Vgg, I used 3Kohm from the Vdd pin to the Vgg pin to bias the chip on. When I wanted to disable the chip, I pulled Vgg to ground with 4 p-channel JFETs in parallel. I did this because I needed to get the S21 of the chip down to < -25dB (i.e. ~55dB on-to-off ratio) to meet system requirements. This required getting the gate voltage down to < 100mV, hence the need for parallel JFETs.
This scheme nominally met the 1us turn-on time. Turn-off was much faster (~200ns). It is possible that the turn-on time could be reduced further by reducing the value of the bypass on Vgg from 100pF to something less, but I have not checked to see if the chip remains stable for values < 100pF.
Thank you very much. You have been very helpful. I have also encountered chips oscillating for certain source and load impedance combinations.