Hello,
I am attempting to test the phase margin of a buck converter according to this video:
Qspice #5: Closed-Loop Frequency Response of DC-DC Converters
However, at approximately midway, it keeps failing, generating the following error:
Time domain 20% complete
Time domain 30% complete
Time domain 40% complete
Time domain 50% complete
Time domain 60% complete
Fatal error: Timestep too small(2.77456e-12) at t=22.1965
Here is the test schematic that I am using:
Synchronous_Buck_Converter_Compensator_Type_III_2z3p.qsch (25.6 KB)
What is odd is that it is taking a very long time to run. A few minutes actually. Is this to be expected?
Can someone please advise how to work around this.
Update:
Updated the circuit to the following version (I added 1nf capacitors in parallel to all switching divices):
Synchronous_Buck_Converter_Compensator_Type_III_2z3p_Modified_Schematic_v1.qsch (28.6 KB)
Now I get this error:
Time domain 10% complete
Time domain 20% complete
Time domain 30% complete
Time domain 40% complete
Time domain 50% complete
Time domain 60% complete
Fatal error: realloc: can’t allocate 671088640 bytes.
Prior to this, I also tested the schematic with these directives (added one directive at a time - bottom most first):
.option trtol=10
.option method=gear
.option maxstep=10
.bode V6 500e-6 1 1e5 1 .options BODEAMPFREQ=0
.meas Fbw find freq when Mag(OpenLoopGain)=1
.meas PhaseMargin find Phase(OpenLoopGain) at Fbw