ACT43750 Bias control without ACT43850-issue

RF Solutions RF All Other (switches, controls, attenuators, ..)
1

We are using ACT43750 for Bias Sequencing our RF PA without using ACT43850 external regulator. The device is stuck in FSM state REG50 Ramp. We are unable to bypass the REG50 Ramp state. It waits for ACT43850 to respond and it eventually goes to REGG Shutdown state. Kindly provide a solution to bypass the ACT43850 REG50 Ramp up state and progress with the FSM.

2

The ACT43750 can be used standalone without the ACT43850. (Note the ACT43850 is no longer available.)
What are you testing the ACT43750 on? Your own PCB design, or a Qorvo evaluation board?
The REG50 Ramp state is intended to start and monitor an external drain regulator. When the ACT43750 enters this state, it releases the PG/VPG open-drain node and waits for the external-regulator power-good condition. The ACT43750 then proceeds to TX Ready state when REGG and REG50 are both considered ready.
For operation without an ACT43850:

  1. Provide the drain voltage externally to the ACT43750 V50/DSW50 power path. The ACT43750 supports drain voltages from 10 V to 55 V.
  2. Pull the ACT43750 PG pin high through an external pull-up resistor to an appropriate logic supply, typically 3.3 V or 5 V within the pin limits. A pull-up is preferable to a hard connection because the ACT43750 must retain the ability to pull PG low in response to a fault.
  3. Ensure that no external circuit holds PG low. PG is an open-drain, wired-OR power-good input/output; an external device pulling it low is interpreted by the ACT43750 as a power-good failure.
  4. Keep ENG/ENTX low during startup, enable REGG, and allow REGG to reach its target voltage.
  5. Verify that the PG node rises after REGG is ready. The FSM should then leave REG50 Ramp and enter TX Ready state.
  6. Only after TX Ready is confirmed should you enable the drain switch or calibration sequence.

On the ACT43750 standalone eval board (EVK3) the PG pin 18 is pulled up to 5V via a 10K resistor. See EVK3 User Guide.

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3

Thank you for your suggestion. Our issue is resolved now. It was caused due to PG pin being pulled low by another external circuit on the board.