About the issue of dw1000PCB

[color=#333333][size=small][font=Arial,]This is my old PCB layout.[/font][/size][/color][color=#333333][size=small][font=Arial,]The power supply used TPS73601 to supply 3.3v to DW1000, and ap2121a to supply 3.0v to TCXO, but the test result of this old version is like this.[/font][/size][/color]
[color=#333333][size=small][font=Arial,]I tested the receiving and receiving situation at close range, channel 5, PRF64M, PLEN1024, PAC32, 110k.[/font][/size][/color]
[color=#333333][size=small][font=Arial,]Transmission is very poor, only the antenna at a certain Angle, will occasionally receive.[/font][/size][/color]
[color=#333333][size=small][font=Arial,]The Error reported by SYS_STATUS is either the Receiver PHY Header Error or the Receiver Reed Solomon Frame Sync Loss.[/font][/size][/color]
[color=#333333][size=small][font=Arial,]I carefully read the aph001 manual, and I felt that I was not doing EMI. Electromagnetic interference caused signal distortion.[/font][/size][/color]
[color=#333333][size=small][font=Arial,]I’m ready to make a new version, but there may be other reasons, so I ask everyone for help.[/font][/size][/color]

[color=#333333][size=small][font=Arial,]Thanks to decawave for giving me such a good platform! :heart: [/font][/size][/color]

Your power supply traces from C47-C52 to U3 are a little longer than ideal. I know it’s not easy to fit those parts in but anything you can do to lower the inductance on those lines is good. Possible improvements to this that I can think of:

Use smaller parts so that they can fit in closer to the IC.
Close up the gap between the two rows of capacitors.
Move the vias from the side of C47-49 to in between them, this moves C49 and C47 a tiny bit further away but allows you yo move C50-52 closer.
Thicken up the power traces from the caps to the chip as much as possible and then neck them down when you get close to the chip. That goes for all power and ground signals.
I can’t see how power gets to C46 to start with, I’m assuming it’s a plane or flood of some sort.

And on the RF side you have the same trace thickness into B1 as you do on the output. That means that the impedance matching must be wrong on one side or the other. Whichever is wrong you need to fix.

There looks to be a via in the pad for C53

[color=#333333][size=small][font=Arial,]Thank you so much AndyA!!![/font][/size][/color]

[color=#333333][size=small][font=Arial,]I found the reason, in a post a few days ago(https://www.decawave.com/decaforum/showthread.php?tid=1122), you answered how crystal tuned, let me be inspired!I tried it myself, and it worked, and when I tuned it, the reception was normal, and it was a long way off.Thank you very much. There are some problems in my PCB layout, which can be further optimized.I’m going to really test the whole thing.I’m too excited to speak now.Thank you very, very much.[/font][/size][/color]

Hi Apricity,

As Andy mentions, it’s always good to use smaller components as it allows you to get decoupling caps closer to the IC, etc., etc. This is also important for the external loop filter components - I have seen customers have problems with spurious emissions when certifying due to RF PLL harmonics coming from these external components. Using small components allows you to limit the area of the circuit and lower power in the harmonics. Basically, use 0201 (or at least 0402) components with the DW1000 wherever possible.

Looks like you might be using a TCXO aswell? Beware that you need to filter any noise on VDDBATT from the 3V3 rail when using a TCXO with DW1000 in order to avoid packet loss. See APH001 for more detail on this.