*$ * LM25037 ***************************************************************************** * (C) Copyright 2016 Texas Instruments Incorporated. All rights reserved. ***************************************************************************** ** This model is designed as an aid for customers of Texas Instruments. ** TI and its licensors and suppliers make no warranties, either expressed ** or implied, with respect to this model, including the warranties of ** merchantability or fitness for a particular purpose. The model is ** provided solely on an "as is" basis. The entire risk as to its quality ** and performance is with the customer ***************************************************************************** * * This model is subject to change without notice. Texas Instruments * Incorporated is not responsible for updating this model. * ***************************************************************************** * ** Released by: WEBENCH Design Center, Texas Instruments Inc. * Part: LM25037 * Date: 10NOV2016 * Model Type: TRANSIENT * Simulator: PSPICE * Simulator Version: 16.2.0.p001 * EVM Order Number:LM25037 Evaluation Board * EVM Users Guide: SNVA352C–July 2008–Revised May 2013 * Datasheet: SNVS572C -January 8, 2010 * * Model Version: Final 1.20 * ***************************************************************************** * * Updates: * * Final 1.00 * Release to Web. * * Final 1.10 * Bugfix in the Error Amplifier * * Final 1.20 * Digital spice implemenation were modified to make the model * compatible to other spice simulators. * ***************************************************************************** * * Model Usage Notes: * * 1. The following features have been modeled * a. Switching Characteristics and variation with VIN * b. Line UVLO, Soft-Start * c. Current limit, Hiccup * 2. Temperature effects are not modeled. * 3. Ground node has been tied to 0V internally. This model can not be used for inverting topologies. * ***************************************************************************** .SUBCKT LM25037_TRANS COMP CS FB OUTA OUTB RAMP REF RES RT1 RT2 SS UVLO VCC VIN E_RT2gen T2GEN 0 VALUE { if (V(PWM_ENABLE)>3, 2, 0) } C_C_enrt1 RT1VAL 0 25nF G_I_SStart REF SS VALUE { if (V(normal_op) > 1, min(100uA, V(REF) - + V(SS)), 0) } X_U11 CSSTART CSSTART_INV INV R_R_STDBY2g 0 STDBY 10K X_UVLO_latch 0 0 SHUT_DN NORMAL_OP EN_OUTS M_UN0001 TFFRSH R_R_Toff2G1 0 RT2 1G R_Rramp2G 0 RAMP 1G V_I_ramp1 RAMP RAMPVAL DC 0 AC 0 0 E_RT1gen T1GEN 0 VALUE { if (V(PWM_ENABLE)>3, 2, 0) } R_VREG1_Rstdby2G 0 STDBY 1G I_VREG1_Iref VREG1_VREFLIM REF DC 10mA E_VREG1_E_REFready REFREADY 0 VALUE { if (V(REF,REFREG_VAL) + + 0.4*V(REFREADY)/5 < 0, 0, 5.0) } E_VREG1_ABM5 VREG1_VCCREG 0 VALUE { IF (V(STDBY) > 1, min(V(VIN), + V(VCCREG_VAL)), 0) } R_VREG1_Rstdby2G1 0 VCCREG_VAL 1G E_VREG1_ABM4 VREG1_VREFREG 0 VALUE { IF (V(STDBY) > 1, min(V(VIN), + V(REFREG_VAL)), 0) } I_VREG1_IVcc VREG1_VCCLIM VCC DC 20mA R_VREG1_Rref2G 0 REFREG_VAL 1G D_VREG1_DVcc1 VREG1_VCCREG VREG1_VCCLIM DIDEAL R_VREG1_RVIN2G 0 VIN 1G D_VREG1_DVcc2 VCC VREG1_VCCLIM DIDEAL D_VREG1_Dref1 VREG1_VREFREG VREG1_VREFLIM DIDEAL D_VREG1_Dref2 REF VREG1_VREFLIM DIDEAL E_VREG1_E_VCCready VCCREADY 0 VALUE { if (V(VCC,VCCREG_VAL) + + 0.5*V(VCCREADY)/5 < 0, 0, 5.0) } C_C_enrt2 RT2VAL 0 25nF E_V_posrail POSRAIL 0 VALUE {1 * V(REF)} D_D_EAopen_drain COMP EABUF DIDEAL R_R_pullup COMP REF 5K G_G_erramp NEGRAIL VEA V1P25 FB 100u V_V_pwmoffset COMP PWMREF 1.0Vdc R_R_EAgain NEGRAIL VEA 60Meg V_V1p25 V1P25 0 1.25Vdc E_EAbuf EABUF 0 VALUE { min(V(VEA, 0), V(SS)) } C_C_EApole VEA NEGRAIL 4pF D_D_EAmax VEA POSRAIL DIDEAL D_D_EAmin NEGRAIL VEA DIDEAL V_V_negrail NEGRAIL 0 10mV G_CSDischg CSVAL 0 VALUE { if (V(CSDISCH) > 200mV-100*I(V_I_CS), if + (V(pwmref) < 30mV & V(QA)+V(QB) > 1, V(CS)/1K, V(CS)/21), 0) } V_I_CS CS CSVAL DC 0 AC 0 0 V_VCSlim CSLIM 0 0.255Vdc G_RampDischg RAMPVAL 0 VALUE { if (V(RAMPDISCH) > 200mV-100*I(V_I_ramp1), V(RAMP)/5, 0)} E_Euvlo UVLOREADY 0 VALUE { if (V(UVLO,REF1P25) > 0, 5.0, 0) } R_R_SS2gnd 0 SS 1G E_Aclock TOSCUS 0 VALUE { + max(1m*V(TOFFns)+0.162*V(RT1)/max(1000*I(V_IRT1),1m), 500*(1-V(PWM_enable))) + } X_RS1_Usawctl2 CLK RS1_SELECTA RS1_SETA AND2 X_RS1_latchA RS1 RS1 RS1_RESET_DIG RS1_SETA QA M_UN0002 SRLATCHSHP X_RS1_U9 PWM_ENABLE RS1_ENINV INV X_RS1_latchB RS1 RS1 RS1_RESET_DIG RS1_SETB QB M_UN0003 SRLATCHSHP RS1 RS1 0 300 RS2 RS2 0 300 X_RS1_U912 CLK CLKB INV X_RS1_U10 PWM_ENABLE CLKB RS1_SELECTA RS1_SELECTB TFFS X_RS1_init RS1_ENINV RSTLATCH RS1_RESET_DIG OR2 X_RS1_Usawctl3 RS1_SELECTB CLK RS1_SETB AND2 R_Rpwmref2G 0 PWMREF 1G X_CSlat RS2 RS2 CSSTART CSEND CSDISCH M_UN0004 SRLATCHSHP E_Adeadtime TOFFNS 0 VALUE { max(5*V(RT2)/max(1000*I(V_IRT2),1m),50) + } E_EdrvA DRVA 0 VALUE { if (V(QA,0) < 0.5, 0, if (V(QA,0) < 3.0 , + V(VCC)*V(QA,0)/2.5, V(VCC))) } V_ref1p25 REF1P25 0 1.25Vdc X_ramplat RS2 RS2 CLK RAMPEND RAMPDISCH M_UN0005 SRLATCHSHP V_ref0p45 REF0P45 0 0.45Vdc R_R_Tosc2G 0 TOSCUS 1Meg R_RdrvA DRVA OUTA 2 X_en_out VCCREADY REFREADY UVLOREADY NORMAL_OP AND3 X_U10 TMAX PWMDUTY CURLIM RSTLATCH OR3 G_SS_short SS 0 VALUE { if (V(EN_OUTS) > 1.0,V(SS)/1G, max(-5A, + min(5A,V(SS)))) } E_EdrvB DRVB 0 VALUE { if (V(QB,0) < 0.5, 0, if (V(QB,0) < 3.0 , + V(VCC)*V(QB,0)/2.5, V(VCC))) } R_R_enrt2 T2GEN RT2VAL 1 R_R_Toff2G 0 TOFFNS 1Meg R_R_Toff2G2 0 RT1 1G G_Guvlo REF UVLO VALUE { if (V(UVLOREADY,0) > 1.0, 22uA, 0) } X_U9 PWM_ENABLE PWMOFF INV R_RCS2G 0 CS 1G V_VCCreg_val VCCREG_VAL 0 7.7Vdc V_IRT2 RT2VAL RT2 +PULSE 0 0 X_init3 CSOVER PWMOFF CSEND OR2 X_BlankDLY CLK CSSTART DELAYAB PARAMS: + DELAY=65n E_Estdby STDBY 0 VALUE { if (V(UVLO,REF0P45) + 0.1*V(STDBY)/5 > 0, 5.0, + 0) } R_R_Tosc2G1 0 SAWTOOTH 1Meg E_curlim_comparator CURLIM 0 VALUE { if(V(CS, CSLIM) + 100u*V(curlim)/5 + > 0, 5, 0) } X_OSC1_U2 OSC1_VCO_DLY OSC1_VCO_SQ_D OSC1_ENABLE OSC1_DDTIME AND3 X_OSC1_Uclk OSC1_DDTIME_INV OSC1_DDTIME_DLY CLK AND2 X_OSC1_TmaxW OSC1_DDTIME OSC1_DDTIME_DLY DELAYAB PARAMS: + DELAY=15ns R_OSC1_Rsaw2G SAWTOOTH 0 10G X_OSC1_VCO OSC1_MHZ OSC1_VCO_SIN VCO_sin PARAMS: Fcenter=500k + Frange=500K Vmin=0 Vmax=1 Phase=0 X_OSC1_DLY1_U56 OSC1_VCO_INV OSC1_DLY1_B0 OSC1_DLY1_A0 AND2 X_OSC1_DLY1_U45 OSC1_DLY1_DLYA1 OSC1_DLY1_C1 OSC1_DLY1_DLY1 OR2 X_OSC1_DLY1_U39 OSC1_DLY1_NOTB9 OSC1_DLY1_DLY8 OSC1_DLY1_C9 AND2 X_OSC1_DLY1_U36 OSC1_DLY1_DLY8 OSC1_DLY1_B9 OSC1_DLY1_A9 AND2 X_OSC1_DLY1_U17 OSC1_DLY1_DLYA3 OSC1_DLY1_C3 OSC1_DLY1_DLY3 OR2 X_OSC1_DLY1_U28 OSC1_DLY1_DLY5 OSC1_DLY1_B6 OSC1_DLY1_A6 AND2 R_OSC1_DLY1_A2D0_R_tst2G 0 OSC1_DLY1_TESTVAL_0 1G R_OSC1_DLY1_A2D0_R_B2G 0 OSC1_DLY1_A2D0_BVAL 1G E_OSC1_DLY1_A2D0_subtract OSC1_DLY1_RESID_0 0 VALUE { + if(V(OSC1_DLY1_RESID_1) > V(OSC1_DLY1_TESTVAL_0), + V(OSC1_DLY1_RESID_1)-V(OSC1_DLY1_TESTVAL_0), V(OSC1_DLY1_RESID_1)) } X_OSC1_DLY1_A2D0_B_dig OSC1_DLY1_A2D0_BVAL OSC1_DLY1_B0 BUF E_OSC1_DLY1_A2D0_genbit OSC1_DLY1_A2D0_BVAL 0 VALUE { + if(V(OSC1_DLY1_RESID_1) > V(OSC1_DLY1_TESTVAL_0), 5, 0) } E_OSC1_DLY1_A2D0_divby2 OSC1_DLY1_TESTVAL_0 0 VALUE {0.5 * + V(OSC1_DLY1_TESTVAL_1)} R_OSC1_DLY1_A2D0_R_resid2G 0 OSC1_DLY1_RESID_0 1G X_OSC1_DLY1_dly7 OSC1_DLY1_A7 OSC1_DLY1_DLYA7 DELAYAB + PARAMS: + DELAY=32ns X_OSC1_DLY1_U55 OSC1_DLY1_NOTB4 OSC1_DLY1_DLY3 OSC1_DLY1_C4 AND2 X_OSC1_DLY1_U33 OSC1_DLY1_DLYA2 OSC1_DLY1_C2 OSC1_DLY1_DLY2 OR2 X_OSC1_DLY1_U21 OSC1_DLY1_DLYA11 OSC1_DLY1_C11 OSC1_VCO_DLY OR2 X_OSC1_DLY1_U27 OSC1_DLY1_NOTB10 OSC1_DLY1_DLY9 OSC1_DLY1_C10 AND2 X_OSC1_DLY1_U24 OSC1_DLY1_DLY9 OSC1_DLY1_B10 OSC1_DLY1_A10 AND2 R_OSC1_DLY1_A2D2_R_tst2G 0 OSC1_DLY1_TESTVAL_2 1G R_OSC1_DLY1_A2D2_R_B2G 0 OSC1_DLY1_A2D2_BVAL 1G E_OSC1_DLY1_A2D2_subtract OSC1_DLY1_RESID_2 0 VALUE { + if(V(OSC1_DLY1_RESID_3) > V(OSC1_DLY1_TESTVAL_2), + V(OSC1_DLY1_RESID_3)-V(OSC1_DLY1_TESTVAL_2), V(OSC1_DLY1_RESID_3)) } X_OSC1_DLY1_A2D2_B_dig OSC1_DLY1_A2D2_BVAL OSC1_DLY1_B2 BUF E_OSC1_DLY1_A2D2_genbit OSC1_DLY1_A2D2_BVAL 0 VALUE { + if(V(OSC1_DLY1_RESID_3) > V(OSC1_DLY1_TESTVAL_2), 5, 0) } E_OSC1_DLY1_A2D2_divby2 OSC1_DLY1_TESTVAL_2 0 VALUE {0.5 * + V(OSC1_DLY1_TESTVAL_3)} R_OSC1_DLY1_A2D2_R_resid2G 0 OSC1_DLY1_RESID_2 1G R_OSC1_DLY1_A2D7_R_tst2G 0 OSC1_DLY1_TESTVAL_7 1G R_OSC1_DLY1_A2D7_R_B2G 0 OSC1_DLY1_A2D7_BVAL 1G E_OSC1_DLY1_A2D7_subtract OSC1_DLY1_RESID_7 0 VALUE { + if(V(OSC1_DLY1_RESID_8) > V(OSC1_DLY1_TESTVAL_7), + V(OSC1_DLY1_RESID_8)-V(OSC1_DLY1_TESTVAL_7), V(OSC1_DLY1_RESID_8)) } X_OSC1_DLY1_A2D7_B_dig OSC1_DLY1_A2D7_BVAL OSC1_DLY1_B7 BUF E_OSC1_DLY1_A2D7_genbit OSC1_DLY1_A2D7_BVAL 0 VALUE { + if(V(OSC1_DLY1_RESID_8) > V(OSC1_DLY1_TESTVAL_7), 5, 0) } E_OSC1_DLY1_A2D7_divby2 OSC1_DLY1_TESTVAL_7 0 VALUE {0.5 * + V(OSC1_DLY1_TESTVAL_8)} R_OSC1_DLY1_A2D7_R_resid2G 0 OSC1_DLY1_RESID_7 1G X_OSC1_DLY1_U52 OSC1_DLY1_DLY3 OSC1_DLY1_B4 OSC1_DLY1_A4 AND2 R_OSC1_DLY1_A2D5_R_tst2G 0 OSC1_DLY1_TESTVAL_5 1G R_OSC1_DLY1_A2D5_R_B2G 0 OSC1_DLY1_A2D5_BVAL 1G E_OSC1_DLY1_A2D5_subtract OSC1_DLY1_RESID_5 0 VALUE { + if(V(OSC1_DLY1_RESID_6) > V(OSC1_DLY1_TESTVAL_5), + V(OSC1_DLY1_RESID_6)-V(OSC1_DLY1_TESTVAL_5), V(OSC1_DLY1_RESID_6)) } X_OSC1_DLY1_A2D5_B_dig OSC1_DLY1_A2D5_BVAL OSC1_DLY1_B5 BUF E_OSC1_DLY1_A2D5_genbit OSC1_DLY1_A2D5_BVAL 0 VALUE { + if(V(OSC1_DLY1_RESID_6) > V(OSC1_DLY1_TESTVAL_5), 5, 0) } E_OSC1_DLY1_A2D5_divby2 OSC1_DLY1_TESTVAL_5 0 VALUE {0.5 * + V(OSC1_DLY1_TESTVAL_6)} R_OSC1_DLY1_A2D5_R_resid2G 0 OSC1_DLY1_RESID_5 1G X_OSC1_DLY1_U41 OSC1_DLY1_DLYA5 OSC1_DLY1_C5 OSC1_DLY1_DLY5 OR2 X_OSC1_DLY1_U46 OSC1_DLY1_B1 OSC1_DLY1_NOTB1 INV R_OSC1_DLY1_A2D3_R_tst2G 0 OSC1_DLY1_TESTVAL_3 1G R_OSC1_DLY1_A2D3_R_B2G 0 OSC1_DLY1_A2D3_BVAL 1G E_OSC1_DLY1_A2D3_subtract OSC1_DLY1_RESID_3 0 VALUE { + if(V(OSC1_DLY1_RESID_4) > V(OSC1_DLY1_TESTVAL_3), + V(OSC1_DLY1_RESID_4)-V(OSC1_DLY1_TESTVAL_3), V(OSC1_DLY1_RESID_4)) } X_OSC1_DLY1_A2D3_B_dig OSC1_DLY1_A2D3_BVAL OSC1_DLY1_B3 BUF E_OSC1_DLY1_A2D3_genbit OSC1_DLY1_A2D3_BVAL 0 VALUE { + if(V(OSC1_DLY1_RESID_4) > V(OSC1_DLY1_TESTVAL_3), 5, 0) } E_OSC1_DLY1_A2D3_divby2 OSC1_DLY1_TESTVAL_3 0 VALUE {0.5 * + V(OSC1_DLY1_TESTVAL_4)} R_OSC1_DLY1_A2D3_R_resid2G 0 OSC1_DLY1_RESID_3 1G X_OSC1_DLY1_U57 OSC1_DLY1_DLYA0 OSC1_DLY1_C0 OSC1_DLY1_DLY0 OR2 X_OSC1_DLY1_U51 OSC1_DLY1_NOTB8 OSC1_DLY1_DLY7 OSC1_DLY1_C8 AND2 X_OSC1_DLY1_U18 OSC1_DLY1_B3 OSC1_DLY1_NOTB3 INV X_OSC1_DLY1_U48 OSC1_DLY1_DLY7 OSC1_DLY1_B8 OSC1_DLY1_A8 AND2 X_OSC1_DLY1_U37 OSC1_DLY1_DLYA9 OSC1_DLY1_C9 OSC1_DLY1_DLY9 OR2 X_OSC1_DLY1_U29 OSC1_DLY1_DLYA6 OSC1_DLY1_C6 OSC1_DLY1_DLY6 OR2 R_OSC1_DLY1_A2D11_R_tst2G 0 OSC1_DLY1_TESTVAL_11 1G R_OSC1_DLY1_A2D11_R_B2G 0 OSC1_DLY1_A2D11_BVAL 1G E_OSC1_DLY1_A2D11_subtract OSC1_DLY1_RESID_11 0 VALUE { + if(V(OSC1_DLY1_DLY_SCALED) > V(OSC1_DLY1_TESTVAL_11), + V(OSC1_DLY1_DLY_SCALED)-V(OSC1_DLY1_TESTVAL_11), V(OSC1_DLY1_DLY_SCALED)) } X_OSC1_DLY1_A2D11_B_dig OSC1_DLY1_A2D11_BVAL OSC1_DLY1_B11 BUF E_OSC1_DLY1_A2D11_genbit OSC1_DLY1_A2D11_BVAL 0 VALUE { + if(V(OSC1_DLY1_DLY_SCALED) > V(OSC1_DLY1_TESTVAL_11), 5, 0) } E_OSC1_DLY1_A2D11_divby2 OSC1_DLY1_TESTVAL_11 0 VALUE {0.5 * + V(OSC1_DLY1_MAXVAL)} R_OSC1_DLY1_A2D11_R_resid2G 0 OSC1_DLY1_RESID_11 1G X_OSC1_DLY1_U13 OSC1_DLY1_DLYA7 OSC1_DLY1_C7 OSC1_DLY1_DLY7 OR2 X_OSC1_DLY1_U34 OSC1_DLY1_B2 OSC1_DLY1_NOTB2 INV X_OSC1_DLY1_U22 OSC1_DLY1_B11 OSC1_DLY1_NOTB11 INV R_OSC1_DLY1_A2D8_R_tst2G 0 OSC1_DLY1_TESTVAL_8 1G R_OSC1_DLY1_A2D8_R_B2G 0 OSC1_DLY1_A2D8_BVAL 1G E_OSC1_DLY1_A2D8_subtract OSC1_DLY1_RESID_8 0 VALUE { + if(V(OSC1_DLY1_RESID_9) > V(OSC1_DLY1_TESTVAL_8), + V(OSC1_DLY1_RESID_9)-V(OSC1_DLY1_TESTVAL_8), V(OSC1_DLY1_RESID_9)) } X_OSC1_DLY1_A2D8_B_dig OSC1_DLY1_A2D8_BVAL OSC1_DLY1_B8 BUF E_OSC1_DLY1_A2D8_genbit OSC1_DLY1_A2D8_BVAL 0 VALUE { + if(V(OSC1_DLY1_RESID_9) > V(OSC1_DLY1_TESTVAL_8), 5, 0) } E_OSC1_DLY1_A2D8_divby2 OSC1_DLY1_TESTVAL_8 0 VALUE {0.5 * + V(OSC1_DLY1_TESTVAL_9)} R_OSC1_DLY1_A2D8_R_resid2G 0 OSC1_DLY1_RESID_8 1G X_OSC1_DLY1_U25 OSC1_DLY1_DLYA10 OSC1_DLY1_C10 OSC1_DLY1_DLY10 OR2 X_OSC1_DLY1_U42 OSC1_DLY1_B5 OSC1_DLY1_NOTB5 INV X_OSC1_DLY1_U53 OSC1_DLY1_DLYA4 OSC1_DLY1_C4 OSC1_DLY1_DLY4 OR2 X_OSC1_DLY1_U58 OSC1_DLY1_B0 OSC1_DLY1_NOTB0 INV X_OSC1_DLY1_dly1 OSC1_DLY1_A1 OSC1_DLY1_DLYA1 DELAYAB + PARAMS: + DELAY=0.5ns X_OSC1_DLY1_U38 OSC1_DLY1_B9 OSC1_DLY1_NOTB9 INV X_OSC1_DLY1_U49 OSC1_DLY1_DLYA8 OSC1_DLY1_C8 OSC1_DLY1_DLY8 OR2 X_OSC1_DLY1_dly3 OSC1_DLY1_A3 OSC1_DLY1_DLYA3 DELAYAB + PARAMS: + DELAY=2ns X_OSC1_DLY1_U30 OSC1_DLY1_B6 OSC1_DLY1_NOTB6 INV R_OSC1_DLY1_R_max2g 0 OSC1_DLY1_MAXVAL 1G R_OSC1_DLY1_A2D10_R_tst2G 0 OSC1_DLY1_TESTVAL_10 1G R_OSC1_DLY1_A2D10_R_B2G 0 OSC1_DLY1_A2D10_BVAL 1G E_OSC1_DLY1_A2D10_subtract OSC1_DLY1_RESID_10 0 VALUE { + if(V(OSC1_DLY1_RESID_11) > V(OSC1_DLY1_TESTVAL_10), + V(OSC1_DLY1_RESID_11)-V(OSC1_DLY1_TESTVAL_10), V(OSC1_DLY1_RESID_11)) } X_OSC1_DLY1_A2D10_B_dig OSC1_DLY1_A2D10_BVAL OSC1_DLY1_B10 BUF E_OSC1_DLY1_A2D10_genbit OSC1_DLY1_A2D10_BVAL 0 VALUE { + if(V(OSC1_DLY1_RESID_11) > V(OSC1_DLY1_TESTVAL_10), 5, 0) } E_OSC1_DLY1_A2D10_divby2 OSC1_DLY1_TESTVAL_10 0 VALUE {0.5 * + V(OSC1_DLY1_TESTVAL_11)} R_OSC1_DLY1_A2D10_R_resid2G 0 OSC1_DLY1_RESID_10 1G X_OSC1_DLY1_dly2 OSC1_DLY1_A2 OSC1_DLY1_DLYA2 DELAYAB + PARAMS: + DELAY=1ns X_OSC1_DLY1_dly11 OSC1_DLY1_A11 OSC1_DLY1_DLYA11 DELAYAB + PARAMS: + DELAY=512ns X_OSC1_DLY1_U26 OSC1_DLY1_B10 OSC1_DLY1_NOTB10 INV R_OSC1_DLY1_A2D4_R_tst2G 0 OSC1_DLY1_TESTVAL_4 1G R_OSC1_DLY1_A2D4_R_B2G 0 OSC1_DLY1_A2D4_BVAL 1G E_OSC1_DLY1_A2D4_subtract OSC1_DLY1_RESID_4 0 VALUE { + if(V(OSC1_DLY1_RESID_5) > V(OSC1_DLY1_TESTVAL_4), + V(OSC1_DLY1_RESID_5)-V(OSC1_DLY1_TESTVAL_4), V(OSC1_DLY1_RESID_5)) } X_OSC1_DLY1_A2D4_B_dig OSC1_DLY1_A2D4_BVAL OSC1_DLY1_B4 BUF E_OSC1_DLY1_A2D4_genbit OSC1_DLY1_A2D4_BVAL 0 VALUE { + if(V(OSC1_DLY1_RESID_5) > V(OSC1_DLY1_TESTVAL_4), 5, 0) } E_OSC1_DLY1_A2D4_divby2 OSC1_DLY1_TESTVAL_4 0 VALUE {0.5 * + V(OSC1_DLY1_TESTVAL_5)} R_OSC1_DLY1_A2D4_R_resid2G 0 OSC1_DLY1_RESID_4 1G E_OSC1_DLY1_MAXDLY OSC1_DLY1_MAXVAL 0 VALUE { 2**12 } X_OSC1_DLY1_U54 OSC1_DLY1_B4 OSC1_DLY1_NOTB4 INV X_OSC1_DLY1_dly5 OSC1_DLY1_A5 OSC1_DLY1_DLYA5 DELAYAB + PARAMS: + DELAY=8ns X_OSC1_DLY1_U14 OSC1_DLY1_B7 OSC1_DLY1_NOTB7 INV X_OSC1_DLY1_dly0 OSC1_DLY1_A0 OSC1_DLY1_DLYA0 DELAYAB + PARAMS: + DELAY=0.25ns X_OSC1_DLY1_U50 OSC1_DLY1_B8 OSC1_DLY1_NOTB8 INV X_OSC1_DLY1_dly9 OSC1_DLY1_A9 OSC1_DLY1_DLYA9 DELAYAB + PARAMS: + DELAY=128ns R_OSC1_DLY1_A2D1_R_tst2G 0 OSC1_DLY1_TESTVAL_1 1G R_OSC1_DLY1_A2D1_R_B2G 0 OSC1_DLY1_A2D1_BVAL 1G E_OSC1_DLY1_A2D1_subtract OSC1_DLY1_RESID_1 0 VALUE { + if(V(OSC1_DLY1_RESID_2) > V(OSC1_DLY1_TESTVAL_1), + V(OSC1_DLY1_RESID_2)-V(OSC1_DLY1_TESTVAL_1), V(OSC1_DLY1_RESID_2)) } X_OSC1_DLY1_A2D1_B_dig OSC1_DLY1_A2D1_BVAL OSC1_DLY1_B1 BUF E_OSC1_DLY1_A2D1_genbit OSC1_DLY1_A2D1_BVAL 0 VALUE { + if(V(OSC1_DLY1_RESID_2) > V(OSC1_DLY1_TESTVAL_1), 5, 0) } E_OSC1_DLY1_A2D1_divby2 OSC1_DLY1_TESTVAL_1 0 VALUE {0.5 * + V(OSC1_DLY1_TESTVAL_2)} R_OSC1_DLY1_A2D1_R_resid2G 0 OSC1_DLY1_RESID_1 1G X_OSC1_DLY1_dly6 OSC1_DLY1_A6 OSC1_DLY1_DLYA6 DELAYAB + PARAMS: + DELAY=16ns X_OSC1_DLY1_U47 OSC1_DLY1_NOTB1 OSC1_DLY1_DLY0 OSC1_DLY1_C1 AND2 X_OSC1_DLY1_U19 OSC1_DLY1_NOTB3 OSC1_DLY1_DLY2 OSC1_DLY1_C3 AND2 X_OSC1_DLY1_dly10 OSC1_DLY1_A10 OSC1_DLY1_DLYA10 DELAYAB + PARAMS: + DELAY=256ns R_OSC1_DLY1_A2D9_R_tst2G 0 OSC1_DLY1_TESTVAL_9 1G R_OSC1_DLY1_A2D9_R_B2G 0 OSC1_DLY1_A2D9_BVAL 1G E_OSC1_DLY1_A2D9_subtract OSC1_DLY1_RESID_9 0 VALUE { + if(V(OSC1_DLY1_RESID_10) > V(OSC1_DLY1_TESTVAL_9), + V(OSC1_DLY1_RESID_10)-V(OSC1_DLY1_TESTVAL_9), V(OSC1_DLY1_RESID_10)) } X_OSC1_DLY1_A2D9_B_dig OSC1_DLY1_A2D9_BVAL OSC1_DLY1_B9 BUF E_OSC1_DLY1_A2D9_genbit OSC1_DLY1_A2D9_BVAL 0 VALUE { + if(V(OSC1_DLY1_RESID_10) > V(OSC1_DLY1_TESTVAL_9), 5, 0) } E_OSC1_DLY1_A2D9_divby2 OSC1_DLY1_TESTVAL_9 0 VALUE {0.5 * + V(OSC1_DLY1_TESTVAL_10)} R_OSC1_DLY1_A2D9_R_resid2G 0 OSC1_DLY1_RESID_9 1G X_OSC1_DLY1_U44 OSC1_DLY1_DLY0 OSC1_DLY1_B1 OSC1_DLY1_A1 AND2 X_OSC1_DLY1_dly4 OSC1_DLY1_A4 OSC1_DLY1_DLYA4 DELAYAB + PARAMS: + DELAY=4ns X_OSC1_DLY1_U35 OSC1_DLY1_NOTB2 OSC1_DLY1_DLY1 OSC1_DLY1_C2 AND2 X_OSC1_DLY1_U23 OSC1_DLY1_NOTB11 OSC1_DLY1_DLY10 OSC1_DLY1_C11 AND2 X_OSC1_DLY1_U16 OSC1_DLY1_DLY2 OSC1_DLY1_B3 OSC1_DLY1_A3 AND2 X_OSC1_DLY1_U15 OSC1_DLY1_NOTB7 OSC1_DLY1_DLY6 OSC1_DLY1_C7 AND2 X_OSC1_DLY1_U12 OSC1_DLY1_DLY6 OSC1_DLY1_B7 OSC1_DLY1_A7 AND2 X_OSC1_DLY1_dly8 OSC1_DLY1_A8 OSC1_DLY1_DLYA8 DELAYAB + PARAMS: + DELAY=64ns X_OSC1_DLY1_U43 OSC1_DLY1_NOTB5 OSC1_DLY1_DLY4 OSC1_DLY1_C5 AND2 X_OSC1_DLY1_U32 OSC1_DLY1_DLY1 OSC1_DLY1_B2 OSC1_DLY1_A2 AND2 X_OSC1_DLY1_U20 OSC1_DLY1_DLY10 OSC1_DLY1_B11 OSC1_DLY1_A11 AND2 X_OSC1_DLY1_U59 OSC1_DLY1_NOTB0 OSC1_VCO_INV OSC1_DLY1_C0 AND2 X_OSC1_DLY1_U40 OSC1_DLY1_DLY4 OSC1_DLY1_B5 OSC1_DLY1_A5 AND2 E_OSC1_DLY1_dly_scale OSC1_DLY1_DLY_SCALED 0 VALUE {4 * V(TOFFNS)} X_OSC1_DLY1_U31 OSC1_DLY1_NOTB6 OSC1_DLY1_DLY5 OSC1_DLY1_C6 AND2 R_OSC1_DLY1_A2D6_R_tst2G 0 OSC1_DLY1_TESTVAL_6 1G R_OSC1_DLY1_A2D6_R_B2G 0 OSC1_DLY1_A2D6_BVAL 1G E_OSC1_DLY1_A2D6_subtract OSC1_DLY1_RESID_6 0 VALUE { + if(V(OSC1_DLY1_RESID_7) > V(OSC1_DLY1_TESTVAL_6), + V(OSC1_DLY1_RESID_7)-V(OSC1_DLY1_TESTVAL_6), V(OSC1_DLY1_RESID_7)) } X_OSC1_DLY1_A2D6_B_dig OSC1_DLY1_A2D6_BVAL OSC1_DLY1_B6 BUF E_OSC1_DLY1_A2D6_genbit OSC1_DLY1_A2D6_BVAL 0 VALUE { + if(V(OSC1_DLY1_RESID_7) > V(OSC1_DLY1_TESTVAL_6), 5, 0) } E_OSC1_DLY1_A2D6_divby2 OSC1_DLY1_TESTVAL_6 0 VALUE {0.5 * + V(OSC1_DLY1_TESTVAL_7)} R_OSC1_DLY1_A2D6_R_resid2G 0 OSC1_DLY1_RESID_6 1G E_OSC1_enable OSC1_ENABLE 0 VALUE { max(min(1K*V(OSC1_MHZ)-5, 5), 0) + } X_OSC1_U4 OSC1_VCO_SQ OSC1_VCO_SQ_D BUF X_OSC1_Umax OSC1_DDTIME_INV OSC1_DDTIME_DLY TMAX NOR2 X_OSC1_U5 OSC1_DDTIME OSC1_DDTIME_INV INV X_OSC1_Usawctl2 OSC1_ENABLE OSC1_CLK_INV OSC1_SAWCTL AND2 E_OSC1_pulsgen OSC1_VCO_SQ 0 VALUE { if (V(OSC1_VCO_SIN)>1u, 0, 5) } R_OSC1_Rvco2g OSC1_VCO_SQ 0 10G C_OSC1_C_saw SAWTOOTH 0 1000pF E_OSC1_VCOctl OSC1_MHZ 0 VALUE { 1/V(TOSCUS) } X_OSC1_U3 OSC1_VCO_SQ OSC1_VCO_INV INV G_OSC1_I_SAW 0 SAWTOOTH VALUE { if(V(OSC1_SAWCTL) > 3, 1m/V(TOSCUS), + -V(SAWTOOTH)) } X_OSC1_U6 OSC1_DDTIME OSC1_CLK_INV INV E_PWMenable PWM_ENABLE 0 VALUE { if(V(en_outs) > 2 & V(pwmref) > 0, 5, + 0) } X_stdby_inv STDBY SHUT_DN INV R_RdrvB DRVB OUTB 2 X_U12 CSSTART_INV RSTLATCH CSOVER AND2 G_I_SStop SS 0 VALUE { if(V(en_outs) < 1, 0, if(V(normal_op) < 1, + min(100uA, V(SS)), 0)) } R_RdmyUVLO 0 UVLOREADY 10K V_VREFreg_val REFREG_VAL 0 5.0Vdc R_R_enrt1 T1GEN RT1VAL 1 X_init1 TMAX PWMOFF RAMPEND OR2 V_IRT1 RT1VAL RT1 +PULSE 0 0 R_RstubRES RES 0 1G E_PWM_comparator PWMDUTY 0 VALUE { if(V(RAMP, PWMREF)+100u*V(pwmduty)/5 + > 0, 5, 0) } .ENDS LM25037_TRANS *$ .model DIDEAL d + is=1e-014 + n=0.1 + cjo=1e-013 + rs=0.1 *$ .subckt TON_FSW_U4_S1 1 2 3 4 S_U4_S1 3 4 1 2 _U4_S1 RS_U4_S1 1 2 1G .MODEL _U4_S1 VSWITCH Roff=1m Ron=1e9 Voff=0.9V Von=0.1V .ends TON_FSW_U4_S1 *$ .MODEL Dcmpd2838 D ( IS=17.8n RS=0.168 BV=75.0 IBV=10.0n CJO=663f TT=5.76n M=0.333 N=2.12 ) *$ .MODEL MBRB3030CTL D (is=3.8914e-09 rs=0.00582261 n=0.57753 eg=0.624214 + xti=0.752162 cjo=6.22779e-09 + vj=0.4 m=0.533092 fc=0.5 tt=0 kf=0 af=1) *$ .MODEL DI_SBL4030PT D ( IS=10.9u RS=1.53m BV=30.0 IBV=1.00m + CJO=1.33n M=0.333 N=1.08 TT=14.4n ) *$ .SUBCKT BAT54 1 3 R1 1 3 3.6E+07 D1 1 3 DBAT54 .MODEL DBAT54 D( + IS = 2.117E-07 + N = 1.016 + BV = 36 + IBV = 1.196E-06 + RS = 2.637 + CJO = 1.114E-11 + VJ = 0.2013 + M = 0.3868 + FC = 0 + TT = 0 + EG = 0.69 + XTI = 2) .ENDS *$ .SUBCKT INV I0 O + PARAMS: VDD=5 VSS=0 VTHRESH=2.5 E_ABMGATE YINT 0 VALUE {{IF(V(I0) > {VTHRESH} , + {VSS},{VDD})}} RINT YINT O 1 CINT O 0 1n .ENDS *$ .SUBCKT TFFRSH CLK D R S Q QB PARAMS: VDD=5 VSS=0 VTHRESH=1.5 X1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 0 X2 CLK CLKdel CLKint AND2 PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} GQ 0 Qint VALUE = {IF(V(S) > {VTHRESH},5,IF(V(R) > {VTHRESH},-5, IF(V(CLKint)> {VTHRESH}, + IF(V(D)> {VTHRESH},5,-5),0)))} CQint Qint 0 1n IC ={VSS} RQint Qint 0 1000MEG D_D10 Qint MY5 D_D1 V1 MY5 0 {VDD} D_D11 MYVSS Qint D_D1 V2 MYVSS 0 {VSS} EQ Qqq 0 Qint 0 1 X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD=5 VSS=0 VTHRESH=1.5 DELAY =0 RQq Qqqd1 Q 1 EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})} RQb Qbr Qb 1 Cdummy1 Q 0 1nF Cdummy2 QB 0 1nF .MODEL D_D1 D( IS=1e-15 TT=10p Rs=0.05 N=.1 ) .ENDS *$ .SUBCKT AND2 I0 I1 O + PARAMS: VDD=5 VSS=0 VTHRESH=2.5 E_ABMGATE YINT 0 VALUE {{IF(V(I0) > {VTHRESH} & + V(I1) > {VTHRESH},{VDD},{VSS})}} RINT YINT O 1n CINT O 0 1n .ENDS *$ .SUBCKT TFFS T clk Q QB X_U2 T N13476 INV PARAMS: VDD=5 VSS=0 VTHRESH=2.5 X_U3 QB T N13827 AND2 PARAMS: VDD=5 VSS=0 VTHRESH=2.5 X_U1 Q QB clk N13749 0 0 dffsr_shpbasic_gen PARAMS: VDD=5 VSS=0 + VTHRESH=2.5 X_U5 N13827 N13867 N13749 OR2 PARAMS: VDD=5 VSS=0 VTHRESH=2.5 X_U4 N13476 Q N13867 AND2 PARAMS: VDD=5 VSS=0 VTHRESH=2.5 .ENDS *$ .subckt dffsr_shpbasic_gen q qb clk d r s params: vdd=5 vss=0 vthresh=2.5 x1 clk clkdel inv_delay_basic_gen params: vdd={vdd} vss={vss} vthresh= + {vthresh} delay = 0 x2 clk clkdel clkint and2 params: vdd={vdd} vss={vss} vthresh= + {vthresh} gq 0 qint value = {if(v(s) > {vthresh},5,if(v(r) > {vthresh},-5, if(v(clkint)> + {vthresh}, + if(v(d)> {vthresh},5,-5),0)))} cqint qint 0 1n IC={vss} rqint qint 0 1000meg d_d10 qint my5 d_d1 v1 my5 0 {vdd} d_d11 myvss qint d_d1 v2 myvss 0 {vss} eq qqq 0 qint 0 1 x3 qqq qqqd1 buf_delay_basic_gen params: vdd=5 vss=0 vthresh=2.5 delay = 0 rqq qqqd1 q 1 eqb qbr 0 value = {if( v(q) > {vthresh}, {vss},{vdd})} rqb qbr qb 1 cdummy1 q 0 1nf cdummy2 qb 0 1nf .model d_d1 d + is=1e-015 + tt=1e-011 + rs=0.05 + n=0.1 .ends dffsr_shpbasic_gen *$ .SUBCKT INV_DELAY_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n E_ABMGATE1 YINT1 0 VALUE {{IF(V(A) > {VTHRESH} , + {VDD},{VSS})}} RINT YINT1 YINT2 1 CINT YINT2 0 {DELAY*1.443} E_ABMGATE2 YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} , + {VSS},{VDD})}} RINT2 YINT3 Y 1 CINT2 Y 0 1n .ENDS INV_DELAY_BASIC_GEN *$ .SUBCKT OR2 A B Y + PARAMS: VDD=5 VSS=0 VTHRESH=2.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | + V(B) > {VTHRESH},{VDD},{VSS})}} RINT YINT Y 1 CINT Y 0 1n .ENDS *$ .SUBCKT AND3 A B C Y + PARAMS: VDD=5 VSS=0 VTHRESH=2.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & + V(B) > {VTHRESH} & + V(C) > {VTHRESH},{VDD},{VSS})}} RINT YINT Y 1 CINT Y 0 1n .ENDS *$ .SUBCKT OR3 A B C Y + PARAMS: VDD=5 VSS=0 VTHRESH=2.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | + V(B) > {VTHRESH} | + V(C) > {VTHRESH},{VDD},{VSS})}} RINT YINT Y 1 CINT Y 0 1n .ENDS *$ .SUBCKT BUF A Y + PARAMS: VDD=5 VSS=0 VTHRESH=2.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} , + {VDD},{VSS})}} RINT YINT Y 1 CINT Y 0 1n .ENDS *$ .SUBCKT NOR2 A B Y + PARAMS: VDD=5 VSS=0 VTHRESH=2.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | + V(B) > {VTHRESH},{VSS},{VDD})}} RINT YINT Y 1 CINT Y 0 1n .ENDS *$ .SUBCKT Si7892BDP 4 1 2 M1 3 1 2 2 NMOS W=7013158u L=0.25u M2 2 1 2 4 PMOS W=7013158u L=0.25u R1 4 3 RTEMP 15E-4 CGS 1 2 2500E-12 DBD 2 4 DBD .MODEL NMOS NMOS ( LEVEL = 3 TOX = 5E-8 + RS = 15E-4 RD = 0 NSUB = 2.81E17 + KP = 1.2E-5 UO = 650 + VMAX = 0 XJ = 5E-7 KAPPA = 1E-1 + ETA = 1E-4 TPG = 1 + IS = 0 LD = 0 + CGSO = 0 CGDO = 0 CGBO = 0 + NFS = 0.8E12 DELTA = 0.1) .MODEL PMOS PMOS ( LEVEL = 3 TOX = 5E-8 +NSUB = 3E16 TPG = -1) .MODEL DBD D (CJO=1250E-12 VJ=0.38 M=0.29 +FC=0.1 IS=1E-12 TT=5E-8 N=1 BV=30.2) .MODEL RTEMP RES (TC1=5E-3 TC2=5.5E-6) .ENDS *$ .subckt PULLDOWN A + params: VALUE=300 Rpull A 0 {VALUE} .ends *$ .subckt vco_sin in out Params: Fcenter=1k Frange=50 Vmin=0 Vmax=5 +phase=0 Rin in 0 1G Rtable table 0 1G Etable table 0 Value {LIMIT(2*V(in)-1,-1,1)} V_time time_a 0 pwl(0s 0V 1s 1V) Esin out 0 +Value {sin(6.28318*(Fcenter*V(time_a)+Frange*IDt(V(table)))+phase*(3.14159/180))} .ends *$ .SUBCKT PL140-100L SCT P1 P2 S1 S2 PCT E_M14 LP1X2 LP1X3 VALUE { 0.999*15uH*V(SCT,LS2X0)/7.5uH } E_M42 LS2X1 LS2X2 VALUE { 0.999*15uH*V(PCT,LP2X0)/30uH } E_M34 LS1X2 LS1X3 VALUE { 0.999*7.5uH*V(SCT,LS2X0)/7.5uH } E_M31 LS1X0 LS1X1 VALUE { 0.999*15uH*V(P1,LP1X0)/30uH } E_M13 LP1X1 LP1X2 VALUE { 0.999*15uH*V(S1,LS1X0)/7.5uH } E_M23 LP2X1 LP2X2 VALUE { 0.999*15uH*V(S1,LS1X0)/7.5uH } R_Rs1 SCT LS1X3 2m E_M24 LP2X2 LP2X3 VALUE { 0.999*15uH*V(SCT,LS2X0)/7.5uH } R_Rp1 PCT LP1X3 12m E_M32 LS1X1 LS1X2 VALUE { 0.999*15uH*V(PCT,LP2X0)/30uH } E_M43 LS2X2 LS2X3 VALUE { 0.999*7.5uH*V(S1,LS1X0)/7.5uH } E_M41 LS2X0 LS2X1 VALUE { 0.999*15uH*V(P1,LP1X0)/30uH } R_Rp2 P2 LP2X3 12m R_Rs2 S2 LS2X3 2m E_M21 LP2X0 LP2X1 VALUE { 0.999*30uH*V(P1,LP1X0)/30uH } E_M12 LP1X0 LP1X1 VALUE { 0.999*30uH*V(PCT,LP2X0)/30uH } L_L3 S1 LS1X0 7.5uH L_L4 SCT LS2X0 7.5uH L_L1 P1 LP1X0 30uH L_L2 PCT LP2X0 30uH .ENDS *$ .subckt d_d1 1 2 d1 1 2 dd1 .model dd1 d + is=1e-015 + tt=1e-011 + rs=0.05 + n=0.001 .ends d_d1 *$ .SUBCKT DELAYAB A B PARAMS: DELAY = 10n C_C2 0 N466082 {DELAY*1.443} X_D5 N466082 N465791 D_D1 E_ABM1 N465791 0 VALUE { IF(V(N465945)>2.5, 5, 0) } X_D4 A N465945 D_D1 R_R1 A N465945 1 E_ABM2 B 0 VALUE { IF(V(N466082)>2.5, 5, 0) } C_C1 0 N465945 {DELAY*1.443} R_R2 N465791 N466082 1 .ENDS *$ .SUBCKT SRLATCHSHP D CLK R S Q QB PARAMS: VDD=3.5 VSS=0 VTHRESH=1.75 X2 CLK CLK CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} GQ 0 Qint VALUE = {IF(V(S) > {VTHRESH},5,IF(V(R) > {VTHRESH},-5, IF(V(CLKint)> {VTHRESH}, + IF(V(D)> {VTHRESH},5,-5),0)))} CQint Qint 0 1n IC={VSS} RQint Qint 0 1000MEG D_D10 Qint MY5 D_D1 V1 MY5 0 {VDD} D_D11 MYVSS Qint D_D1 V2 MYVSS 0 {VSS} EQ Qqq 0 Qint 0 1 X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 20n RQq Qqqd1 Q 1 EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})} RQb Qbr Qb 1 Cdummy1 Q 0 1nF Cdummy2 QB 0 1nF .MODEL D_D1 D( IS=1e-15 TT=10p Rs=0.05 N=.1 ) .ENDS *$ .SUBCKT AND2_BASIC_GEN A B Y PARAMS: VDD=5 VSS=0 VTHRESH=1.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & + V(B) > {VTHRESH},{VDD},{VSS})}} RINT YINT Y 1 CINT Y 0 1n .ENDS AND2_BASIC_GEN *$ .SUBCKT BUF_DELAY_BASIC_GEN A Y PARAMS: VDD=5 VSS=0 VTHRESH=1.5 DELAY = 10n E_ABMGATE1 YINT1 0 VALUE {{IF(V(A) > {VTHRESH} , + {VDD},{VSS})}} RINT YINT1 YINT2 1 CINT YINT2 0 {DELAY*1.443} E_ABMGATE2 YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} , + {VDD},{VSS})}} RINT2 YINT3 Y 1 CINT2 Y 0 1n .ENDS BUF_DELAY_BASIC_GEN *$ .SUBCKT Si7456DP 4 1 2 M1 3 1 2 2 NMOS W=4357764u L=0.50u M2 2 1 2 4 PMOS W=4357764u L=0.40u R1 4 3 RTEMP 17E-3 CGS 1 2 1450E-12 DBD 2 4 DBD .MODEL NMOS NMOS ( LEVEL = 3 TOX = 7E-8 + RS = 2.67E-3 RD = 0 NSUB = 2.23E17 + KP = 2.5E-5 UO = 650 + VMAX = 0 XJ = 5E-7 KAPPA = 75E-2 + ETA = 1E-4 TPG = 1 + IS = 0 LD = 0 + CGSO = 0 CGDO = 0 CGBO = 0 + NFS = 0.8E12 DELTA = 0.1) .MODEL PMOS PMOS ( LEVEL = 3 TOX = 7E-8 +NSUB = 0.6E16 TPG = -1) .MODEL DBD D (CJO=1150E-12 VJ=0.38 M=0.40 +FC=0.1 IS=1E-12 TT=3.15E-8 N=1 BV=100.5) .MODEL RTEMP RES (TC1=7.5E-3 TC2=5.5E-6) .ENDS *$ .SUBCKT CESR IN OUT + PARAMs: C=100u ESR=0.01 C IN 1 {C} RESR 1 OUT {ESR} .ENDS *$