* source LMG3522R030 * * ***************************************************************************** * (C) Copyright 2020 Texas Instruments Incorporated. All rights reserved. ***************************************************************************** ** This model is designed as an aid for customers of Texas Instruments. ** TI and its licensors and suppliers make no warranties, either expressed ** or implied, with respect to this model, including the warranties of ** merchantability or fitness for a particular purpose. The model is ** provided solely on an "as is" basis. The entire risk as to its quality ** and performance is with the customer. ***************************************************************************** * * Released by: Texas Instruments Inc. * Part: LMG3522R030 * Date: 10/04/2022 * Model Type: Transient * Simulator: PSPICE * Simulator Version: 17.4 * Datasheet: https://www.ti.com/lit/gpn/LMG3522R030 * Model Version: Final 2.0 * Release to Web. **************************************************************************** .SUBCKT lmg3522R030 VDD LDO_5V IN RDRV BBSW VNEG OC_B FAULT_B TEMP GND SOURCE DRAIN + PARAMS: Temp_Celsius=160 X_UTOP_U8 GND UTOP_GATE_INT D_D E_UTOP_E8 FAULT_B GND UTOP_N01929 0 1 V_UTOP_U_Ilim1_V36 UTOP_U_Ilim1_N16859418 0 10m X_UTOP_U_Ilim1_U124 UTOP_U_Ilim1_N16889539 UTOP_U_Ilim1_N16890960 + UTOP_U_Ilim1_N16890541 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3 X_UTOP_U_Ilim1_S20 UTOP_IN_DLY_INTREF 0 UTOP_U_Ilim1_N16889841 0 + Current_Limit_UTOP_U_Ilim1_S20 X_UTOP_U_Ilim1_U111 UTOP_U_Ilim1_N16887220 UTOP_U_Ilim1_N16887227 + UTOP_U_Ilim1_ISHORT_RESET OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3 V_UTOP_U_Ilim1_V5 UTOP_U_Ilim1_N16859462 0 95 C_UTOP_U_Ilim1_C17 0 UTOP_U_Ilim1_N16859491 4p TC=0,0 X_UTOP_U_Ilim1_U125 UTOP_U_Ilim1_N16889539 UTOP_U_Ilim1_N16890960 + BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=100n V_UTOP_U_Ilim1_V37 UTOP_U_Ilim1_N16888739 0 10m X_UTOP_U_Ilim1_U100 UTOP_U_Ilim1_N16859356 UTOP_U_Ilim1_N16859379 + BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=100n X_UTOP_U_Ilim1_U92 UTOP_U_Ilim1_N16859491 UTOP_U_Ilim1_N16860466 + UTOP_U_Ilim1_N16859356 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3 C_UTOP_U_Ilim1_C16 0 UTOP_U_Ilim1_N16843199 1n TC=0,0 V_UTOP_U_Ilim1_V38 UTOP_U_Ilim1_N16888723 0 70 X_UTOP_U_Ilim1_U62 UTOP_U_Ilim1_N16843199 UTOP_U_Ilim1_N16887220 + ONE_SHOT PARAMS: T=100 C_UTOP_U_Ilim1_C18 0 UTOP_U_Ilim1_N16889841 1p TC=0,0 X_UTOP_U_Ilim1_U99 UTOP_U_Ilim1_N16792069 UTOP_I_FAULT_Z + BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=50n X_UTOP_U_Ilim1_S18 UTOP_IN_DLY_INTREF 0 UTOP_U_Ilim1_N16843199 0 + Current_Limit_UTOP_U_Ilim1_S18 R_UTOP_U_Ilim1_R21 UTOP_U_Ilim1_N16866694 UTOP_U_Ilim1_N16843199 300k + TC=0,0 X_UTOP_U_Ilim1_U116 UTOP_IN_DLY_INTREF UTOP_U_Ilim1_N16889804 + INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3 X_UTOP_U_Ilim1_U93 UTOP_U_Ilim1_N16859356 UTOP_U_Ilim1_N16859379 + UTOP_U_Ilim1_N16859468 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3 X_UTOP_U_Ilim1_U63 UTOP_PGOOD UTOP_U_Ilim1_N16887227 ONE_SHOT PARAMS: + T=100 X_UTOP_U_Ilim1_U118 UTOP_U_Ilim1_N16889853 UTOP_U_Ilim1_N16889897 + UTOP_U_Ilim1_ILIM_RESET OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3 X_UTOP_U_Ilim1_S17 UTOP_U_Ilim1_N16866362 0 UTOP_U_Ilim1_ONE + UTOP_U_Ilim1_N16866694 Current_Limit_UTOP_U_Ilim1_S17 X_UTOP_U_Ilim1_U112 UTOP_U_Ilim1_N16859468 UTOP_U_Ilim1_ISHORT_RESET + N16888265 UTOP_U_Ilim1_N16792069 SRLATCHSHP_BASIC_GEN PARAMS: VDD=1 VSS=0 + VTHRESH=0.5 X_UTOP_U_Ilim1_S19 UTOP_U_Ilim1_N16889804 0 UTOP_U_Ilim1_ONE + UTOP_U_Ilim1_N16889838 Current_Limit_UTOP_U_Ilim1_S19 X_UTOP_U_Ilim1_U121 UTOP_U_Ilim1_N16890541 UTOP_U_Ilim1_ILIM_RESET + N16890507 UTOP_U_Ilim1_N16890525 SRLATCHSHP_BASIC_GEN PARAMS: VDD=1 VSS=0 + VTHRESH=0.5 V_UTOP_U_Ilim1_V4 UTOP_U_Ilim1_ONE 0 1 R_UTOP_U_Ilim1_R6 UTOP_U_Ilim1_N16859491 UTOP_GATE_DRV_T 72.46e3 + TC=0,0 X_UTOP_U_Ilim1_U114 UTOP_U_Ilim1_N16859491 UTOP_U_Ilim1_N16888720 + UTOP_U_Ilim1_N16889539 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3 X_UTOP_U_Ilim1_U102 UTOP_IN_DLY_INTREF UTOP_U_Ilim1_N16866362 + INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3 X_UTOP_U_Ilim1_U122 UTOP_U_Ilim1_N16890525 UTOP_I_LIMIT_Z + BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=50n X_UTOP_U_Ilim1_U95 UTOP_I_DETECT_T UTOP_U_Ilim1_N16859462 + UTOP_U_Ilim1_N16859418 UTOP_U_Ilim1_N16860466 COMPHYS2_BASIC_GEN PARAMS: VDD=1 + VSS=0 VTHRESH=0.5 T=10 R_UTOP_U_Ilim1_R22 UTOP_U_Ilim1_N16889838 UTOP_U_Ilim1_N16889841 1 + TC=0,0 X_UTOP_U_Ilim1_U119 UTOP_PGOOD UTOP_U_Ilim1_N16889897 ONE_SHOT PARAMS: + T=100 X_UTOP_U_Ilim1_U113 UTOP_I_DETECT_T UTOP_U_Ilim1_N16888723 + UTOP_U_Ilim1_N16888739 UTOP_U_Ilim1_N16888720 COMPHYS2_BASIC_GEN PARAMS: VDD=1 + VSS=0 VTHRESH=0.5 T=10 D_UTOP_U_Ilim1_D66 UTOP_U_Ilim1_N16859491 UTOP_GATE_DRV_T D_D1 X_UTOP_U_Ilim1_U117 UTOP_U_Ilim1_N16889841 UTOP_U_Ilim1_N16889853 + ONE_SHOT PARAMS: T=100 R_UTOP_R22 UTOP_N339734 UTOP_N01929 1k TC=0,0 X_UTOP_U_Fault1_U105 UTOP_U_Fault1_N16802625 UTOP_U_Fault1_N16800340 + BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=110u X_UTOP_U_Fault1_U98 UTOP_U_Fault1_ALL_GOOD UTOP_U_Fault1_ALL_GOOD + UTOP_U_Fault1_N16792825 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3 V_UTOP_U_Fault1_V12 UTOP_U_Fault1_N16809754 0 4.55 X_UTOP_U_Fault1_U112 UTOP_U_Fault1_N16777536 UTOP_U_Fault1_N16777550 + UTOP_U_Fault1_N16780478 UTOP_PGOOD AND3_BASIC_GEN PARAMS: VDD=1 VSS=0 + VTHRESH=500E-3 X_UTOP_U_Fault1_U106 UTOP_U_Fault1_N16800340 UTOP_U_Fault1_N16802625 + UTOP_U_Fault1_N16859326 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3 E_UTOP_U_Fault1_E1 0 UTOP_U_Fault1_ABS_VNEG UTOP_VNEG_14V 0 1 V_UTOP_U_Fault1_V8 UTOP_U_Fault1_N16777668 0 0.5 X_UTOP_U_Fault1_U111 UTOP_U_Fault1_FAULT UTOP_FAULT_Z_TOP + UTOP_U_Fault1_N16785958 UTOP_U_Fault1_ONE UTOP_U_Fault1_N16859326 + UTOP_U_Fault1_N16785958 DFFSR_30N PARAMS: VDD=1 VSS=0 VTHRESH=0.5 X_UTOP_U_Fault1_U100 UTOP_U_Fault1_N16779894 UTOP_N01993 + UTOP_U_Fault1_N16777668 UTOP_U_Fault1_UVLO_VDD COMPHYS2_BASIC_GEN PARAMS: + VDD=1 VSS=0 VTHRESH=0.5 T=10 X_UTOP_U_Fault1_U104 UTOP_U_Fault1_UVLO_LDO UTOP_U_Fault1_N16780478 + INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3 X_UTOP_U_Fault1_U110 UTOP_U_Fault1_N16799356 UTOP_U_Fault1_N16792825 + UTOP_U_Fault1_N16802625 OR2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3 V_UTOP_U_Fault1_V7 UTOP_U_Fault1_N16779894 0 9 X_UTOP_U_Fault1_U109 UTOP_U_Fault1_ALL_GOOD UTOP_U_Fault1_N16785958 + INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3 V_UTOP_U_Fault1_V9 UTOP_U_Fault1_N16820331 0 12.3 X_UTOP_U_Fault1_U102 UTOP_U_Fault1_UVLO_VDD UTOP_U_Fault1_N16777550 + INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3 X_UTOP_U_Fault1_U97 UTOP_PGOOD UTOP_I_FAULT_Z UTOP_U_Fault1_ALL_GOOD + AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3 V_UTOP_U_Fault1_V19 UTOP_U_Fault1_N16799356 0 +PWL 0 0 2n 0 2.5n 1 30n 1 31n 0 X_UTOP_U_Fault1_U103 UTOP_U_Fault1_UVLO_VNEG UTOP_U_Fault1_N16777536 + INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3 V_UTOP_U_Fault1_V10 UTOP_U_Fault1_N16777500 0 0.5 V_UTOP_U_Fault1_V5 UTOP_U_Fault1_ONE 0 1 X_UTOP_U_Fault1_U99 UTOP_U_Fault1_N16820331 UTOP_U_Fault1_ABS_VNEG + UTOP_U_Fault1_N16777500 UTOP_U_Fault1_UVLO_VNEG COMPHYS2_BASIC_GEN PARAMS: + VDD=1 VSS=0 VTHRESH=0.5 T=10 V_UTOP_U_Fault1_V11 UTOP_U_Fault1_N16809735 0 0.790 X_UTOP_U_Fault1_U101 UTOP_U_Fault1_N16809754 UTOP_LDO_5V_INT + UTOP_U_Fault1_N16809735 UTOP_U_Fault1_UVLO_LDO COMPHYS2_BASIC_GEN PARAMS: + VDD=1 VSS=0 VTHRESH=0.5 T=10 E_UTOP_ABM4 UTOP_N339734 0 VALUE { ( V(UTOP_N02173) + *V(UTOP_FAULT_Z_TOP) ) / 1 } E_UTOP_E9 OC_B GND UTOP_I_LIMIT_Z 0 5 X_UTOP_U1 UTOP_IN_INTREF UTOP_IN_DLY_INTREF BUF_DELAY_BASIC_GEN PARAMS: + VDD=1 VSS=0 VTHRESH=0.5 DELAY=25n X_UTOP_U7 UTOP_GATE_INT UTOP_VDDCL D_D C_UTOP_C18 0 UTOP_LDMOS_GATE_TOP 1n TC=0,0 X_UTOP_U_Supplies2_U96 UTOP_LDO_5V_INT UTOP_U_Supplies2_N17939 + UTOP_U_Supplies2_N17859 UTOP_U_Supplies2_LDO_GOOD COMPHYS2_BASIC_GEN PARAMS: + VDD=1 VSS=0 VTHRESH=0.5 T=10 E_UTOP_U_Supplies2_E3 UTOP_N492602 GND UTOP_LDO_5V_INT 0 1 E_UTOP_U_Supplies2_E7 UTOP_U_Supplies2_LPM_B_SHIFTED 0 UTOP_N03195 GND + 1 X_UTOP_U_Supplies2_U95 UTOP_VDD_SHIFTED UTOP_U_Supplies2_N15941 + UTOP_U_Supplies2_N15861 UTOP_U_Supplies2_N20213 COMPHYS2_BASIC_GEN PARAMS: + VDD=1 VSS=0 VTHRESH=0.5 T=10 R_UTOP_U_Supplies2_U_LDO_R5 UTOP_U_Supplies2_U_LDO_VZZ + UTOP_U_Supplies2_U_LDO_VYY 0.5 TC=0,0 R_UTOP_U_Supplies2_U_LDO_R1 UTOP_U_Supplies2_U_LDO_VXX + UTOP_U_Supplies2_ENABLE_LDO 10MEG TC=0,0 R_UTOP_U_Supplies2_U_LDO_R6 UTOP_U_Supplies2_U_LDO_N246201 + UTOP_U_Supplies2_U_LDO_VYY 1 TC=0,0 R_UTOP_U_Supplies2_U_LDO_R2 UTOP_U_Supplies2_U_LDO_N245781 + UTOP_U_Supplies2_U_LDO_VXX 50k TC=0,0 X_UTOP_U_Supplies2_U_LDO_F1 UTOP_U_Supplies2_U_LDO_VZZ UTOP_LDO_5V_INT + UTOP_U_Supplies2_ENABLE_LDO UTOP_U_Supplies2_U_LDO_VYY + LDO_UTOP_U_Supplies2_U_LDO_F1 C_UTOP_U_Supplies2_U_LDO_U1_C2 0 UTOP_U_Supplies2_U_LDO_U1_N05382 1n + TC=0,0 V_UTOP_U_Supplies2_U_LDO_U1_V2 UTOP_U_Supplies2_U_LDO_U1_N29538 0 1.2 R_UTOP_U_Supplies2_U_LDO_U1_R5 UTOP_U_Supplies2_U_LDO_U1_N09745 + UTOP_U_Supplies2_U_LDO_N245781 1k TC=0,0 E_UTOP_U_Supplies2_U_LDO_U1_ABM4 UTOP_U_Supplies2_U_LDO_U1_N09035 0 + VALUE { V(UTOP_U_Supplies2_U_LDO_U1_N05348) + * V(UTOP_LDO_5V_INT) + / (V(UTOP_U_Supplies2_U_LDO_N245745) + 1e-6) } R_UTOP_U_Supplies2_U_LDO_U1_R4 UTOP_U_Supplies2_U_LDO_U1_N09035 + UTOP_U_Supplies2_U_LDO_U1_N05382 1k TC=0,0 V_UTOP_U_Supplies2_U_LDO_U1_V3 UTOP_U_Supplies2_U_LDO_U1_N12664 0 75m R_UTOP_U_Supplies2_U_LDO_U1_R3 UTOP_U_Supplies2_U_LDO_U1_N08164 + UTOP_U_Supplies2_U_LDO_U1_N05348 1k TC=0,0 E_UTOP_U_Supplies2_U_LDO_U1_ABM5 UTOP_U_Supplies2_U_LDO_U1_N09745 0 + VALUE { MIN(V(UTOP_U_Supplies2_U_LDO_U1_N05382), + MAX(V(UTOP_U_Supplies2_ENABLE_LDO), 0)) } C_UTOP_U_Supplies2_U_LDO_U1_C1 0 UTOP_U_Supplies2_U_LDO_U1_N05348 1n + TC=0,0 R_UTOP_U_Supplies2_U_LDO_U1_R2 0 UTOP_U_Supplies2_U_LDO_U1_N05382 1G + TC=0,0 V_UTOP_U_Supplies2_U_LDO_U1_V1 UTOP_U_Supplies2_U_LDO_U1_N29526 0 75m R_UTOP_U_Supplies2_U_LDO_U1_R1 0 UTOP_U_Supplies2_U_LDO_U1_N05348 1G + TC=0,0 E_UTOP_U_Supplies2_U_LDO_U1_ABM6 UTOP_U_Supplies2_U_LDO_U1_N08164 0 + VALUE { IF(V(UTOP_U_Supplies2_U_LDO_U1_N13377)> 0.6 & + V(UTOP_U_Supplies2_U_LDO_U1_N11113) > 0.6, 1.216, 0) } X_UTOP_U_Supplies2_U_LDO_U1_U1 UTOP_U_Supplies2_ENABLE_LDO + UTOP_U_Supplies2_U_LDO_U1_N29538 UTOP_U_Supplies2_U_LDO_U1_N29526 + UTOP_U_Supplies2_U_LDO_U1_N11113 COMPHYS_BASIC_GEN PARAMS: VDD=1 VSS=0 + VTHRESH=0.5 X_UTOP_U_Supplies2_U_LDO_U1_U2 UTOP_U_Supplies2_ENABLE_LDO + UTOP_U_Supplies2_U_LDO_U1_N12783 UTOP_U_Supplies2_U_LDO_U1_N12664 + UTOP_U_Supplies2_U_LDO_U1_N13377 COMPHYS_BASIC_GEN PARAMS: VDD=1 VSS=0 + VTHRESH=0.5 V_UTOP_U_Supplies2_U_LDO_U1_V4 UTOP_U_Supplies2_U_LDO_U1_N12783 0 1.2 C_UTOP_U_Supplies2_U_LDO_U1_C3 0 UTOP_U_Supplies2_U_LDO_N245781 1n + TC=0,0 C_UTOP_U_Supplies2_U_LDO_C3 0 UTOP_U_Supplies2_U_LDO_VYY 1n TC=0,0 E_UTOP_U_Supplies2_U_LDO_ABM1 UTOP_U_Supplies2_U_LDO_N246201 0 VALUE { + MIN(V(UTOP_U_Supplies2_U_LDO_VXX), (V(UTOP_U_Supplies2_U_LDO_VZZ)+0.005)) } C_UTOP_U_Supplies2_U_LDO_C1 UTOP_U_Supplies2_U_LDO_VXX + UTOP_U_Supplies2_ENABLE_LDO 15.9n TC=0,0 R_UTOP_U_Supplies2_U_LDO_R4 UTOP_U_Supplies2_U_LDO_N245745 0 1.216MEG + TC=0,0 C_UTOP_U_Supplies2_U_LDO_C2 UTOP_U_Supplies2_U_LDO_VXX + UTOP_U_Supplies2_U_LDO_N245781 3.18n TC=0,0 R_UTOP_U_Supplies2_U_LDO_R8 UTOP_U_Supplies2_U_LDO_VZZ + UTOP_U_Supplies2_U_LDO_N245745 3.784MEG TC=0,0 V_UTOP_U_Supplies2_V6 UTOP_U_Supplies2_N17939 0 4.5 X_UTOP_U_Supplies2_UBB_U102 UTOP_U_Supplies2_UBB_N17995 + UTOP_U_Supplies2_UBB_N17937 INV_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3 X_UTOP_U_Supplies2_UBB_U14 UTOP_U_Supplies2_UBB_N17671 + UTOP_U_Supplies2_UBB_N17647 D_D V_UTOP_U_Supplies2_UBB_V36 UTOP_U_Supplies2_UBB_N348226 0 10m E_UTOP_U_Supplies2_UBB_ABM1 UTOP_U_Supplies2_UBB_N18091 0 VALUE { (if + (V(UTOP_U_Supplies2_UBB_N17671) < 14,V(UTOP_U_Supplies2_UBB_N17671) ,14)) } X_UTOP_U_Supplies2_UBB_S17 UTOP_U_Supplies2_UBB_N17937 0 + UTOP_U_Supplies2_UBB_N17671 0 BB_Startup_UTOP_U_Supplies2_UBB_S17 C_UTOP_U_Supplies2_UBB_C16 0 UTOP_U_Supplies2_UBB_N336878 1n TC=0,0 R_UTOP_U_Supplies2_UBB_R17 GND BBSW 10 TC=0,0 V_UTOP_U_Supplies2_UBB_V5 UTOP_U_Supplies2_UBB_N348306 0 4 R_UTOP_U_Supplies2_UBB_R21 UTOP_U_Supplies2_UBB_N18091 + UTOP_U_Supplies2_UBB_N336878 1k TC=0,0 C_UTOP_U_Supplies2_UBB_C6 0 UTOP_U_Supplies2_UBB_N17671 2.1n IC=0 + TC=0,0 E_UTOP_U_Supplies2_UBB_E1 0 UTOP_VNEG_14V UTOP_U_Supplies2_UBB_N336878 + 0 1 V_UTOP_U_Supplies2_UBB_V6 UTOP_U_Supplies2_UBB_N17647 0 16 I_UTOP_U_Supplies2_UBB_I3 UTOP_U_Supplies2_UBB_N17647 + UTOP_U_Supplies2_UBB_N17671 DC 100u X_UTOP_U_Supplies2_UBB_U103 UTOP_U_Supplies2_UBB_N348326 + UTOP_U_Supplies2_LDO_GOOD UTOP_U_Supplies2_UBB_N17995 AND2_BASIC_GEN PARAMS: + VDD=1 VSS=0 VTHRESH=500E-3 X_UTOP_U_Supplies2_UBB_U95 UTOP_U_Supplies2_LPM_B_SHIFTED + UTOP_U_Supplies2_UBB_N348306 UTOP_U_Supplies2_UBB_N348226 + UTOP_U_Supplies2_UBB_N348326 COMPHYS2_BASIC_GEN PARAMS: VDD=1 VSS=0 + VTHRESH=0.5 T=10 V_UTOP_U_Supplies2_V37 UTOP_U_Supplies2_N17859 0 100m V_UTOP_U_Supplies2_V5 UTOP_U_Supplies2_N15941 0 9.5 V_UTOP_U_Supplies2_V36 UTOP_U_Supplies2_N15861 0 100m E_UTOP_U_Supplies2_E5 UTOP_U_Supplies2_ENABLE_LDO 0 + UTOP_U_Supplies2_N20213 0 5 E_UTOP_U_Supplies2_E4 VNEG GND UTOP_VNEG_14V 0 1 E_UTOP_U_Supplies2_E2 UTOP_VDD_SHIFTED 0 VDD GND 1 E_UTOP_E6 UTOP_IN_INTREF 0 IN GND 1 X_UTOP_U_Driver_S19 UTOP_U_Driver_GATE_DRVZ 0 UTOP_GATE_INT GND + GaN_Driver_UTOP_U_Driver_S19 X_UTOP_U_Driver_U105 UTOP_U_Driver_N01123 UTOP_GATE_DRV_T + BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=25n X_UTOP_U_Driver_U7 UTOP_U_Driver_N00691 UTOP_U_Driver_N00597 D_D V_UTOP_U_Driver_U_Rsr_V10 UTOP_U_Driver_U_Rsr_N02774 GND 1.2 G_UTOP_U_Driver_U_Rsr_ABMII2 UTOP_U_Driver_N00695 UTOP_GATE_INT VALUE { + (-4040 * V(UTOP_U_Driver_U_Rsr_N15834)* V(UTOP_U_Driver_U_Rsr_N15834) + 0.7444 + * V(UTOP_U_Driver_U_Rsr_N15834) +0.000004303)*6.3 } X_UTOP_U_Driver_U_Rsr_H1 UTOP_U_Driver_U_Rsr_N02774 RDRV + UTOP_U_Driver_U_Rsr_N15834 0 Isr_Conversion_UTOP_U_Driver_U_Rsr_H1 X_UTOP_U_Driver_F5 UTOP_U_Driver_N00597 UTOP_U_Driver_N00695 + UTOP_U_Driver_N00597 UTOP_U_Driver_N00691 GaN_Driver_UTOP_U_Driver_F5 X_UTOP_U_Driver_U103 UTOP_N02535 UTOP_IN_DLY_INTREF + UTOP_U_Driver_N01123 AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3 X_UTOP_U_Driver_U106 UTOP_U_Driver_N01123 UTOP_U_Driver_GATE_DRVZ + INV_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY=25n X_UTOP_U_Driver_S20 UTOP_GATE_DRV_T 0 UTOP_GATE_INT UTOP_U_Driver_N00691 + GaN_Driver_UTOP_U_Driver_S20 V_UTOP_U_Driver_V11 UTOP_U_Driver_N00597 GND 14 X_UTOP_U_Driver_U8 GND UTOP_U_Driver_N00691 D_D X_UTOP_H2 DRAIN UTOP_DRAIN_INT UTOP_I_DETECT_T 0 LMG342X_UTOP_H2 E_UTOP_E11 TEMP GND UTOP_N496067 0 5 V_UTOP_V15 UTOP_N02203 0 5 R_UTOP_U_PWM_Temp_R1 0 UTOP_U_PWM_Temp_INP 100 TC=0,0 G_UTOP_U_PWM_Temp_ABMI1 0 UTOP_U_PWM_Temp_INP VALUE { (60u*TEMP)-0.0012 + } X_UTOP_U_PWM_Temp_COMP1 UTOP_U_PWM_Temp_INP UTOP_U_PWM_Temp_INM + UTOP_U_PWM_Temp_COMP_OUT COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 X_UTOP_U_PWM_Temp_AND1 UTOP_U_PWM_Temp_COMP_OUT UTOP_PGOOD UTOP_N496067 + AND2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3 V_UTOP_U_PWM_Temp_VRAMP1 UTOP_U_PWM_Temp_INM 0 +PULSE 0 1 0 90.8u 100n 90.9u 90.9u V_UTOP_V16 UTOP_N03195 GND 5 X_UTOP_U_GAN_FET UTOP_DRAIN_INT UTOP_GATE_INT UTOP_SOURCE_INT + POWER_N_MOSFET PARAMS:T={Temp_Celsius} R_UTOP_RLDMOS UTOP_SOURCE_INT SOURCE 5m TC=0,0 E_UTOP_E10 UTOP_VDDCL 0 VDD 0 1 C_UTOP_C4 UTOP_DRAIN_INT UTOP_SOURCE_INT 415p IC=0 TC=0,0 R_UTOP_R_probe4 UTOP_VDD_SHIFTED UTOP_N01993 0.1m TC=0,0 C_UTOP_C3 UTOP_GATE_INT UTOP_DRAIN_INT 10p IC=0 TC=0,0 X_UTOP_U97 UTOP_FAULT_Z_TOP UTOP_I_LIMIT_Z UTOP_N02535 AND2_BASIC_GEN + PARAMS: VDD=1 VSS=0 VTHRESH=500E-3 X_UTOP_U118 UTOP_N492602 LDO_5V OUT_CURRENT_CLAMP PARAMS: RSER=1 + IMAX=10M IMIN=10M R_UTOP_R_probet3 UTOP_N02203 UTOP_N02173 0.1m TC=0,0 R_UTOP_R_Pulldown1 IN GND 150k TC=0,0 X_UTOP_U99 UTOP_FAULT_Z_TOP UTOP_N397400 BUF_BASIC_GEN PARAMS: VDD=1 + VSS=0 VTHRESH=0.5 C_UTOP_C17 0 UTOP_N01929 1n TC=0,0 R_UTOP_R23 UTOP_N397400 UTOP_LDMOS_GATE_TOP 1k TC=0,0 .IC V(UTOP_LDMOS_GATE_TOP )=1 .IC V(UTOP_GATE_INT )=0 .ends lmg3522R030 ******************************************************************************************* .subckt Current_Limit_UTOP_U_Ilim1_S20 1 2 3 4 S_UTOP_U_Ilim1_S20 3 4 1 2 _UTOP_U_Ilim1_S20 RS_UTOP_U_Ilim1_S20 1 2 1G .MODEL _UTOP_U_Ilim1_S20 VSWITCH Roff=1e6 Ron=7m Voff=0.0V Von=1.0V .ends Current_Limit_UTOP_U_Ilim1_S20 .subckt Current_Limit_UTOP_U_Ilim1_S18 1 2 3 4 S_UTOP_U_Ilim1_S18 3 4 1 2 _UTOP_U_Ilim1_S18 RS_UTOP_U_Ilim1_S18 1 2 1G .MODEL _UTOP_U_Ilim1_S18 VSWITCH Roff=1e6 Ron=7m Voff=0.0V Von=1.0V .ends Current_Limit_UTOP_U_Ilim1_S18 .subckt Current_Limit_UTOP_U_Ilim1_S17 1 2 3 4 S_UTOP_U_Ilim1_S17 3 4 1 2 _UTOP_U_Ilim1_S17 RS_UTOP_U_Ilim1_S17 1 2 1G .MODEL _UTOP_U_Ilim1_S17 VSWITCH Roff=1e6 Ron=7m Voff=0.0V Von=1.0V .ends Current_Limit_UTOP_U_Ilim1_S17 .subckt Current_Limit_UTOP_U_Ilim1_S19 1 2 3 4 S_UTOP_U_Ilim1_S19 3 4 1 2 _UTOP_U_Ilim1_S19 RS_UTOP_U_Ilim1_S19 1 2 1G .MODEL _UTOP_U_Ilim1_S19 VSWITCH Roff=1e6 Ron=7m Voff=0.0V Von=1.0V .ends Current_Limit_UTOP_U_Ilim1_S19 .subckt LDO_UTOP_U_Supplies2_U_LDO_F1 1 2 3 4 F_UTOP_U_Supplies2_U_LDO_F1 3 4 VF_UTOP_U_Supplies2_U_LDO_F1 1 VF_UTOP_U_Supplies2_U_LDO_F1 1 2 0V .ends LDO_UTOP_U_Supplies2_U_LDO_F1 .subckt BB_Startup_UTOP_U_Supplies2_UBB_S17 1 2 3 4 S_UTOP_U_Supplies2_UBB_S17 3 4 1 2 _UTOP_U_Supplies2_UBB_S17 RS_UTOP_U_Supplies2_UBB_S17 1 2 1G .MODEL _UTOP_U_Supplies2_UBB_S17 VSWITCH Roff=1e6 Ron=7m Voff=0.0V + Von=1.0V .ends BB_Startup_UTOP_U_Supplies2_UBB_S17 .subckt GaN_Driver_UTOP_U_Driver_S19 1 2 3 4 S_UTOP_U_Driver_S19 3 4 1 2 _UTOP_U_Driver_S19 RS_UTOP_U_Driver_S19 1 2 1G .MODEL _UTOP_U_Driver_S19 VSWITCH Roff=1e9 Ron=1m Voff=0.2V Von=0.8V .ends GaN_Driver_UTOP_U_Driver_S19 .subckt Isr_Conversion_UTOP_U_Driver_U_Rsr_H1 1 2 3 4 H_UTOP_U_Driver_U_Rsr_H1 3 4 VH_UTOP_U_Driver_U_Rsr_H1 1 VH_UTOP_U_Driver_U_Rsr_H1 1 2 0V .ends Isr_Conversion_UTOP_U_Driver_U_Rsr_H1 .subckt GaN_Driver_UTOP_U_Driver_F5 1 2 3 4 F_UTOP_U_Driver_F5 3 4 VF_UTOP_U_Driver_F5 5000 VF_UTOP_U_Driver_F5 1 2 0V .ends GaN_Driver_UTOP_U_Driver_F5 .subckt GaN_Driver_UTOP_U_Driver_S20 1 2 3 4 S_UTOP_U_Driver_S20 3 4 1 2 _UTOP_U_Driver_S20 RS_UTOP_U_Driver_S20 1 2 1G .MODEL _UTOP_U_Driver_S20 VSWITCH Roff=1e9 Ron=7m Voff=0.1 Von=0.9 .ends GaN_Driver_UTOP_U_Driver_S20 .subckt LMG342X_UTOP_H2 1 2 3 4 H_UTOP_H2 3 4 VH_UTOP_H2 1 VH_UTOP_H2 1 2 0V .ends LMG342X_UTOP_H2 *.SUBCKT 2to1MUX V1 V2 A out PARAMS: VTHRESH=0.5 *E_MUX OUT 0 VALUE = {IF ( V(A) > {VTHRESH} ,V(V1),V(V2) ) } *.ENDS 2to1MUX .SUBCKT COMP_BASIC_GEN INP INM Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABM Yint 0 VALUE {IF (V(INP) > + V(INM), {VDD},{VSS})} R1 Yint Y 1 C1 Y 0 1n .ENDS COMP_BASIC_GEN .SUBCKT COMPHYS_BASIC_GEN INP INM HYS OUT PARAMS: VDD=1 VSS=0 VTHRESH=0.5 EIN INP1 INM1 INP INM 1 EHYS INP1 INP2 VALUE { IF( V(1) > {VTHRESH},-V(HYS),0) } EOUT OUT 0 VALUE { IF( V(INP2)>V(INM1), {VDD} ,{VSS}) } R1 OUT 1 1 C1 1 0 5.0n RINP1 INP1 0 1K .ENDS COMPHYS_BASIC_GEN .SUBCKT COMPHYS2_BASIC_GEN INP INM HYS OUT PARAMS: VDD=1 VSS=0 VTHRESH=0.5 + T=10 EIN INP1 INM1 INP INM 1 EHYS INM2 INM1 VALUE { IF( V(1) > {VTHRESH},-V(HYS)/2,V(HYS)/2) } EOUT OUT 0 VALUE { IF( V(INP1)>V(INM2), {VDD} ,{VSS}) } R1 OUT 1 1 C1 1 0 {T*1e-9} RINP1 INP1 0 10K RINM2 INM2 0 10K .ENDS COMPHYS2_BASIC_GEN .SUBCKT COMP_BASIC_FAST_GEN INP INM Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABM Yint 0 VALUE {IF(V(INP)>V(INM),{VDD},{VSS})} R1 Yint Y 1 C1 Y 0 1n .ENDS COMP_BASIC_FAST_GEN .SUBCKT delay_basic out inp PARAMS: + tdr = 5e-9 + ttr = 2e-9 + tdf = 5e-9 + ttf = 2e-9 V1 n1 0 DC 1 S1 n1 n2 inp 0 SW1 S2 n2 0 inp 0 SW2 C1 n2 n3 1n E1 n3 0 n5 0 0.5 E2 n4 0 VALUE { IF(V(n2)>0.5, 1, 0) } R2 n4 out 1 C2 out 0 { 0.361*(ttr + ttf)} R3 n4 n5 0.1 C3 n5 0 { 0.361*(ttr + ttf)} .MODEL SW1 VSWITCH Roff={1.44e15*tdr} Ron={1.44e9*tdr} Voff=0.3 Von=0.7 .MODEL SW2 VSWITCH Roff={1.44e15*tdf} Ron={1.44e9*tdf} Voff=0.7 Von=0.3 .ENDS delay_basic .SUBCKT DFFSR_30n Q QB CLK D R S PARAMS: VDD=1 VSS=0 VTHRESH=0.5 ***Set has higher priority in this ** Changed the delay from 7n/10n to 15n/20n to help larger time step simulations **Faster flip-flops require a a smaller time step to simulate X1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 30n X2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} GQ 0 Qint VALUE = {IF(V(R) > {VTHRESH},-5,IF(V(S) > {VTHRESH},5, IF(V(CLKint)> {VTHRESH}, + IF(V(D)> {VTHRESH},5,-5),0)))} CQint Qint 0 1n RQint Qint 0 1000MEG D_D10 Qint MY5 D_D1 V1 MY5 0 {VDD} D_D11 MYVSS Qint D_D1 V2 MYVSS 0 {VSS} EQ Qqq 0 Qint 0 1 X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 20n RQq Qqqd1 Q 1 EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})} RQb Qbr Qb 1 Cdummy1 Q 0 1nF Cdummy2 QB 0 1nF .IC V(Qint) {VSS} .ENDS DFFSR_30n .subckt d_d 1 2 d1 1 2 dd1 .model dd1 d + is=1e-015 + tt=1e-011 + rs=0.05 + n=0.1 .ends d_d .model d_d1 d is=1e-015 tt=1e-011 rs=0.05 n=0.1 .subckt d_d1 1 2 d1 1 2 dd1 .model dd1 d + is=1e-015 + tt=1e-011 + rs=0.05 + n=0.1 .ends d_d1 .subckt D_ideal A C D1 A C DNOM .MODEL DNOM D (TT=10P CJO=1e-18 IS=1e-15 RS=1e-3 N=0.001 ) .ENDS D_ideal .SUBCKT Diode_my 1 2 D1 1 2 DDx *.MODEL DDx D( IS=1e-15 TT=10p Rs=0.05 N=7.8 vj=0.9 ) .MODEL DDx D(BV= 600.0 CJO= 99E-15 M=0.35 N=7.8 VJ= 0.8 ) .ENDS Diode_my .subckt F_to_V Vin Vout LPM V1 2 0 20 SW1 2 0 LPM 0 S_VSWITCH_1 XU3 Vin 0 4 0 VCVS_LIMIT_0 D2 6 Vout D_1N1183_1 C3 0 Vout 10N EVCVS1 6 0 VF1 0 10 QT1 VF1 2 8 Q__PNP_P_1 C2 0 VF1 100N R1 0 VF1 1.1K D1 2 8 D_1N1183_1 C1 4 8 1N .ENDS F_to_V .MODEL D_1N1183_1 D( IS=36N N=1.6 BV=50 IBV=5M RS=2M + CJO=460P VJ=550M M=440M FC=500M TT=434.7N + EG=1.11 XTI=3 KF=0 AF=1 ) .MODEL Q__PNP_P_1 PNP( IS=9.85F NF=1 NR=1 RE=3.18 RC=1 + RB=10 VAF= 1.00000000000000E+0030 VAR= 1.00000000000000E+0030 ISE=0 ISC=0 + ISS=0 NE=1.5 NC=1.5 NS=1 BF=567 + BR=5 IKF=0 IKR=0 CJC=8.96P CJE=9.35P + CJS=0 VJC=615M VJE=991M VJS=750M MJC=330M + MJE=426M MJS=0 TF=531P TR=69N EG=1.11 + KF=0 AF=1 ) .MODEL S_VSWITCH_1 VSWITCH (RON=1U ROFF=1G VON=1 VOFF=0) .SUBCKT VCVS_LIMIT_0 VC+ VC- VOUT+ VOUT- .PARAM GAIN = 25 .PARAM VPOS = 20 .PARAM VNEG = 0 E1 VOUT+ VOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),VPOS,VNEG)} .ENDS VCVS_LIMIT_0 .SUBCKT AND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & + V(B) > {VTHRESH},{VDD},{VSS})}} RINT YINT Y 1 CINT Y 0 1n .ENDS AND2_BASIC_GEN .SUBCKT AND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & + V(B) > {VTHRESH} & + V(C) > {VTHRESH},{VDD},{VSS})}} RINT YINT Y 1 CINT Y 0 1n .ENDS AND3_BASIC_GEN .SUBCKT AND4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & + V(B) > {VTHRESH} & + V(C) > {VTHRESH} & + V(D) > {VTHRESH},{VDD},{VSS})}} RINT YINT Y 1 CINT Y 0 1n .ENDS AND4_BASIC_GEN .SUBCKT NAND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & + V(B) > {VTHRESH},{VSS},{VDD})}} RINT YINT Y 1 CINT Y 0 1n .ENDS NAND2_BASIC_GEN .SUBCKT NAND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & + V(B) > {VTHRESH} & + V(C) > {VTHRESH},{VSS},{VDD})}} RINT YINT Y 1 CINT Y 0 1n .ENDS NAND3_BASIC_GEN .SUBCKT NAND4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} & + V(B) > {VTHRESH} & + V(C) > {VTHRESH} & + V(D) > {VTHRESH},{VSS},{VDD})}} RINT YINT Y 1 CINT Y 0 1n .ENDS NAND4_BASIC_GEN .SUBCKT OR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | + V(B) > {VTHRESH},{VDD},{VSS})}} RINT YINT Y 1 CINT Y 0 1n .ENDS OR2_BASIC_GEN .SUBCKT OR3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | + V(B) > {VTHRESH} | + V(C) > {VTHRESH},{VDD},{VSS})}} RINT YINT Y 1 CINT Y 0 1n .ENDS OR3_BASIC_GEN .SUBCKT OR4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | + V(B) > {VTHRESH} | + V(C) > {VTHRESH} | + V(D) > {VTHRESH},{VDD},{VSS})}} RINT YINT Y 1 CINT Y 0 1n .ENDS OR4_BASIC_GEN .SUBCKT NOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | + V(B) > {VTHRESH},{VSS},{VDD})}} RINT YINT Y 1 CINT Y 0 1n .ENDS NOR2_BASIC_GEN .SUBCKT NOR3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | + V(B) > {VTHRESH} | + V(C) > {VTHRESH},{VSS},{VDD})}} RINT YINT Y 1 CINT Y 0 1n .ENDS NOR3_BASIC_GEN .SUBCKT NOR4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | + V(B) > {VTHRESH} | + V(C) > {VTHRESH} | + V(D) > {VTHRESH},{VSS},{VDD})}} RINT YINT Y 1 CINT Y 0 1n .ENDS NOR4_BASIC_GEN .SUBCKT NOR5_BASIC_GEN A B C D E Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | + V(B) > {VTHRESH} | + V(C) > {VTHRESH} | + V(D) > {VTHRESH} | + V(E) > {VTHRESH},{VSS},{VDD})}} RINT YINT Y 1 CINT Y 0 1n .ENDS NOR5_BASIC_GEN .SUBCKT NOR6_BASIC_GEN A B C D E F Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} | + V(B) > {VTHRESH} | + V(C) > {VTHRESH} | + V(D) > {VTHRESH} | + V(E) > {VTHRESH} | + V(F) > {VTHRESH},{VSS},{VDD})}} RINT YINT Y 1 CINT Y 0 1n .ENDS NOR6_BASIC_GEN .SUBCKT INV_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} , + {VSS},{VDD})}} RINT YINT Y 1 CINT Y 0 1n .ENDS INV_BASIC_GEN .SUBCKT XOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} ^ + V(B) > {VTHRESH},{VDD},{VSS})}} RINT YINT Y 1 CINT Y 0 1n .ENDS XOR2_BASIC_GEN .SUBCKT XNOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} ^ + V(B) > {VTHRESH},{VSS},{VDD})}} RINT YINT Y 1 CINT Y 0 1n .ENDS XNOR2_BASIC_GEN .SUBCKT MUX2_BASIC_GEN A B S Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABMGATE YINT 0 VALUE {{IF(V(S) > {VTHRESH}, + V(B),V(A))}} RINT YINT Y 1 CINT Y 0 1n .ENDS MUX2_BASIC_GEN .SUBCKT BUF_DELAY_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n E_ABMGATE1 YINT1 0 VALUE {{IF(V(A) > {VTHRESH} , + {VDD},{VSS})}} RINT YINT1 YINT2 1 CINT YINT2 0 {DELAY*1.3} E_ABMGATE2 YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} , + {VDD},{VSS})}} RINT2 YINT3 Y 1 CINT2 Y 0 1n .ENDS BUF_DELAY_BASIC_GEN .SUBCKT BUF_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} , + {VDD},{VSS})}} RINT YINT Y 1 CINT Y 0 1n .ENDS BUF_BASIC_GEN .SUBCKT SRLATCHSHP_BASIC_GEN S R Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 **Set has higher priority in this latch GQ 0 Qint VALUE = {IF(V(S) > {VTHRESH},5,IF(V(R)>{VTHRESH},-5, 0))} CQint Qint 0 1n RQint Qint 0 1000MEG D_D10 Qint MY5 D_D1 V1 MY5 0 {VDD} D_D11 MYVSS Qint D_D1 V2 MYVSS 0 {VSS} EQ Qqq 0 Qint 0 1 X3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} RQq Qqqd1 Q 1 EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})} RQb Qbr QB 1 Cdummy1 Q 0 1n Cdummy2 QB 0 1n .IC V(Qint) {VSS} .ENDS SRLATCHSHP_BASIC_GEN .SUBCKT SRLATCHRHP_BASIC_GEN S R Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 **Reset has higher priority in this latch GQ 0 Qint VALUE = {IF(V(R) > {VTHRESH},-5,IF(V(S)>{VTHRESH},5, 0))} CQint Qint 0 1n RQint Qint 0 1000MEG D_D10 Qint MY5 D_D1 V1 MY5 0 {VDD} D_D11 MYVSS Qint D_D1 V2 MYVSS 0 {VSS} EQ Qqq 0 Qint 0 1 X3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} RQq Qqqd1 Q 1 EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})} RQb Qbr QB 1 Cdummy1 Q 0 1n Cdummy2 QB 0 1n .IC V(Qint) {VSS} .ENDS SRLATCHRHP_BASIC_GEN .SUBCKT SBRBLATCHSHP_BASIC_GEN SB RB Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 **Set has higher priority in this latch and active low set and reset - basically NAND based SR latch GQ 0 Qint VALUE = {IF(V(SB) < {VTHRESH},5,IF(V(RB) < {VTHRESH},-5, 0))} CQint Qint 0 1n RQint Qint 0 1000MEG D_D10 Qint MY5 D_D1 V1 MY5 0 {VDD} D_D11 MYVSS Qint D_D1 V2 MYVSS 0 {VSS} EQ Qqq 0 Qint 0 1 X3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} RQq Qqqd1 Q 1 EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})} RQb Qbr QB 1 .IC V(Qint) {VSS} .ENDS SBRBLATCHSHP_BASIC_GEN .SUBCKT SBRBLATCHRHP_BASIC_GEN SB RB Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 **Reset has higher priority in this latch and active low set and reset - basically NAND based SR latch GQ 0 Qint VALUE = {IF(V(RB) < {VTHRESH},-5,IF(V(SB) < {VTHRESH},5, 0))} CQint Qint 0 1n RQint Qint 0 1000MEG D_D10 Qint MY5 D_D1 V1 MY5 0 {VDD} D_D11 MYVSS Qint D_D1 V2 MYVSS 0 {VSS} EQ Qqq 0 Qint 0 1 X3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} RQq Qqqd1 Q 1 EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})} RQb Qbr QB 1 .IC V(Qint) {VSS} .ENDS SBRBLATCHRHP_BASIC_GEN .SUBCKT DFFSBRB_SHPBASIC_GEN Q QB CLK D RB SB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 **Set has higher priority in this **Changed the delay from 7n/10n to 15n/20n to help larger time step simulations **Faster flip-flops require a a smaller time step to simulate X1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 15n X2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} GQ 0 Qint VALUE = {IF(V(SB) < {VTHRESH},5,IF(V(RB)<{VTHRESH},-5, IF(V(CLKint)> {VTHRESH}, + IF(V(D)> {VTHRESH},5,-5),0)))} CQint Qint 0 1n RQint Qint 0 1000MEG D_D10 Qint MY5 D_D1 V1 MY5 0 {VDD} D_D11 MYVSS Qint D_D1 V2 MYVSS 0 {VSS} EQ Qqq 0 Qint 0 1 X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 20n RQq Qqqd1 Q 1 EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})} RQb Qbr Qb 1 Cdummy1 Q 0 1nF Cdummy2 QB 0 1nF .IC V(Qint) {VSS} .ENDS DFFSBRB_SHPBASIC_GEN .SUBCKT DFFSR_SHPBASIC_GEN Q QB CLK D R S PARAMS: VDD=1 VSS=0 VTHRESH=0.5 **Set has higher priority in this **Changed the delay from 7n/10n to 15n/20n to help larger time step simulations **Faster flip-flops require a a smaller time step to simulate X1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 15n X2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} GQ 0 Qint VALUE = {IF(V(S) > {VTHRESH},5,IF(V(R) > {VTHRESH},-5, IF(V(CLKint)> {VTHRESH}, + IF(V(D)> {VTHRESH},5,-5),0)))} CQint Qint 0 1n RQint Qint 0 1000MEG D_D10 Qint MY5 D_D1 V1 MY5 0 {VDD} D_D11 MYVSS Qint D_D1 V2 MYVSS 0 {VSS} EQ Qqq 0 Qint 0 1 X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 20n RQq Qqqd1 Q 1 EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})} RQb Qbr Qb 1 Cdummy1 Q 0 1nF Cdummy2 QB 0 1nF .IC V(Qint) {VSS} .ENDS DFFSR_SHPBASIC_GEN .SUBCKT DFFSBRB_RHPBASIC_GEN Q QB CLK D RB SB PARAMS: VDD=1 VSS=0 VTHRESH=0.5 **Set has higher priority in this **Changed the delay from 7n/10n to 15n/20n to help larger time step simulations **Faster flip-flops require a a smaller time step to simulate X1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 15n X2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} GQ 0 Qint VALUE = {IF(V(RB) < {VTHRESH},-5,IF(V(SB)< {VTHRESH},5, IF(V(CLKint)> {VTHRESH}, + IF(V(D)> {VTHRESH},5,-5),0)))} CQint Qint 0 1n RQint Qint 0 1000MEG D_D10 Qint MY5 D_D1 V1 MY5 0 5 D_D11 0 Qint D_D1 EQ Qqq 0 Qint 0 1 X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 20n RQq Qqqd1 Q 1 EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})} RQb Qbr Qb 1 Cdummy1 Q 0 1nF Cdummy2 QB 0 1nF .IC V(Qint) {VSS} .ENDS DFFSBRB_RHPBASIC_GEN .SUBCKT DFFSR_RHPBASIC_GEN Q QB CLK D R S PARAMS: VDD=1 VSS=0 VTHRESH=0.5 **Set has higher priority in this **Changed the delay from 7n/10n to 15n/20n to help larger time step simulations **Faster flip-flops require a a smaller time step to simulate X1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 15n X2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} GQ 0 Qint VALUE = {IF(V(R) > {VTHRESH},-5,IF(V(S) > {VTHRESH},5, IF(V(CLKint)> {VTHRESH}, + IF(V(D)> {VTHRESH},5,-5),0)))} CQint Qint 0 1n RQint Qint 0 1000MEG D_D10 Qint MY5 D_D1 V1 MY5 0 {VDD} D_D11 MYVSS Qint D_D1 V2 MYVSS 0 {VSS} EQ Qqq 0 Qint 0 1 X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH} DELAY = 20n RQq Qqqd1 Q 1 EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})} RQb Qbr Qb 1 Cdummy1 Q 0 1nF Cdummy2 QB 0 1nF .IC V(Qint) {VSS} .ENDS DFFSR_RHPBASIC_GEN .SUBCKT MONOPOS_PS in Q Qn PARAMS: PW=1u **** SPM_Mono_POS *************************************************************************************** * FUNCTION: SHORT TIME PULSE GENERATOR AT NEG INPUT EDGE * INPUTS/OUTPUTS: ONE DIGITAL INPUT: A, TWO DIG OUTPUT PINS: Q Qn * DESCRIPTION: CREATE A PW PULSE WIDTH AT -VE EDGE OF INPUT, PULSE WIDTH OF INPUT NEEDS TO BE GREATER THAN PW PARAMETER VALUE ********************** ****buffer********* *RA in 0 1e11 *CA in 0 0.01pF *VS VSUP 0 DC 1 **** boolean ************ *EBUF1 Y1 0 VALUE={IF(V(in) > .5 , 1, 0)} *ROUTpp1 Y1 0 1e11 **** add delay lines **** *XNSW1 Y2 Y1 0 NSW_PS PARAMS: RONval={(PW+1e-15)/(1e-12*0.693)} VTHval=0.5 *XPSW1 Y2 Y1 VSUP PSW_PS PARAMS: RONval={(PW+1e-15)/(1e-12*0.693)} VTHval=0.5 *CDEL1 Y2 0 1pF *ETHRESH Y3 0 VALUE={IF(V(Y2) > 0.5, 0, 1)} *ROUTp Y3 0 1e11 * ************add rise and fall ***** **XNSW2 Y4 Y3 0 NSW_PS PARAMS: RONval=(1e-12/1e-12*2.3) VTHval=0.5 **XPSW2 Y4 Y3 VSUP PSW_PS PARAMS: RONval=(1e-12/1e-12*2.3) VTHval=0.5 **CDEL2 Y4 0 1pF ************XOR2*********** *EXOR2 P 0 VALUE={IF(V(in) > 0.5 ^ V(Y3) > .5, 1, 0)} *ROUTpp2 P 0 1e11 **********AND************ *EAND2 Y5 0 VALUE={IF(V(in) > 0.5 & V(P) > 0.5 , 0, 1)} *ROUTpp3 Y5 0 1e11 * add rise and fall ***** *XNSW3 Q Y5 0 NSW_PS PARAMS: RONval=(1e-9/1e-12*2.3) VTHval=0.5 *XPSW3 Q Y5 VSUP PSW_PS PARAMS: RONval=(1e-9/1e-12*2.3) VTHval=0.5 *ROUTq Q 0 1e11 ***********end of AND2******************** * add rise and fall + inversion ***** *XNSW4 Qn Q 0 NSW_PS PARAMS: RONval=(1e-9/1e-12*2.3) VTHval=0.5 *XPSW4 Qn Q VSUP PSW_PS PARAMS: RONval=(1e-9/1e-12*2.3) VTHval=0.5 *ROUTqn Qn 0 1e11 *******************************new take on delay************* VS VSUP 0 DC 1 GIN VSUP YA VALUE={IF(V(IN)>0.5, V(VSUP)/1000K, 0)} GDIS YA 0 VALUE={IF(V(IN)>0.5,0, V(YA)/1m)} CIN YA 0 1n IC=0 RIN YA 0 1e11 EABM1 YTD 0 VALUE={IF(V(YA)> {PW*1000}, 1, 0)} RYTD YTD 0 1e11 EXOR P 0 VALUE={IF(V(YTD) > 0.5 ^ V(IN) > .5, 1, 0)} ROUTpp2 P 0 1e11 EAND1 Q1 0 VALUE={ IF(V(P)>0.5 & V(IN)>0.5, 1, 0)} Ro1 Q1 Q 1m Co1 Q 0 1p ROUT2 Q 0 1e11 EAND2 Qn1 0 VALUE={ IF(V(Q)>0.5, 0, 1)} Ro2 Qn1 Qn 1m Co2 Qn 0 1p ROUT4 Qn 0 1e11 .ENDS MONOPOS_PS .SUBCKT LDCR 1 2 PARAMS: L=1u DCR=20m L1 1 INT1 {L} R1 INT1 2 {DCR} .ENDS LDCR .SUBCKT CESR 1 2 PARAMS: C=10u ESR=2m ESL=1n C1 1 INT1 {C} R1 INT1 INT2 {ESR} L1 INT2 2 {ESL} .ENDS CESR .SUBCKT multiplier V1 V2 OUT E_MULT OUT 0 VALUE = { V(V1) *V(V2) } .ENDS multiplier .SUBCKT 2to1MUX V1 V2 A out PARAMS: VTHRESH=0.5 E_MUX OUT 0 VALUE = {IF ( V(A) > {VTHRESH} ,V(V1),V(V2) ) } .ENDS 2to1MUX .SUBCKT COMPHYS_BASIC_GEN_NORC INP INM HYS OUT PARAMS: VDD=1 VSS=0 VTHRESH=0.5 EIN INP1 INM1 INP INM 1 EHYS INP1 INP2 VALUE { IF( V(1) > {VTHRESH},-V(HYS),0) } EOUT OUT 0 VALUE { IF( V(INP2)>V(INM1), {VDD} ,{VSS}) } R1 OUT 1 1 C1 1 0 1n *RINP1 INP1 0 1K RINP1 INP1 0 1000K .ENDS COMPHYS_BASIC_GEN_NORC .SUBCKT COMP_HYS IN_POS IN_NEG HYS OUT X_U1 IN_POS N00153 OUT COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 E_ABM2 N00234 0 VALUE { V(IN_NEG)+ + +(-V(OUT)*V(HYS)) } R_R1 N00234 N00153 1 C_C1 0 N00153 1n .ENDS COMP_HYS .subckt VCVS_Limit VCP VCN VOUTP VOUTN PARAMS: Gain = -1 * Voltage-Controlled Voltage Source with Limits + Vpos = 20m Vneg = -20m E1 VOUTP VOUTN VALUE={LIMIT(Gain*V(VCP,VCN),Vpos,Vneg)} .ends VCVS_Limit *.SUBCKT INV_DELAY_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n *E_ABMGATE1 YINT1 0 VALUE {{IF(V(A) > {VTHRESH} , *+ {VDD},{VSS})}} *RINT YINT1 YINT2 1 *CINT YINT2 0 {DELAY*1.3} *E_ABMGATE2 YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} , *+ {VDD},{VSS})}} *RINT2 YINT3 Y 1 *CINT2 Y 0 1n *.ENDS INV_DELAY_BASIC_GEN .SUBCKT INV_DELAY_BASIC_GEN A Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 10n E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH} , + {VSS},{VDD})}} RINT YINT Y 1 CINT Y 0 {DELAY*1.3} .ENDS INV_DELAY_BASIC_GEN .SUBCKT VARICAP 1 2 CTRL R1 1 3 1u VC 3 4 0 EBC 4 2 Value = {(1/v(CTRL))*v(INT) } GINT 0 INT Value ={I(VC)} CINT INT 0 1 Rdum INT 0 10E10 .ENDS VARICAP .SUBCKT ONE_SHOT IN OUT + PARAMs: T=100 S_S1 MEAS 0 RESET2 0 S1 E_ABM1 CH 0 VALUE { if( V(IN)>0.5 | V(OUT)>0.5,1,0) } R_R2 RESET2 RESET 0.1 E_ABM3 OUT 0 VALUE { if( V(MEAS)<0.5 & V(CH)>0.5,1,0) } R_R1 MEAS CH {T} C_C2 0 RESET2 1.4427n C_C1 0 MEAS 1.4427n E_ABM2 RESET 0 VALUE { if(V(CH)<0.5,1,0) } .MODEL S1 VSWITCH Roff=1e9 Ron=1.0 Voff=0.25V Von=0.75V .ENDS ONE_SHOT .SUBCKT OUT_CURRENT_CLAMP IN OUT +PARAMS: RSER = 1 IMAX = 10M IMIN = 10M GRESP OUTx OUT VALUE = {LIMIT(V(OUTx,OUT)/RSER,IMAX,-IMIN)} GRESN IN OUTx VALUE = {-V(IN,OUTx)/RSER} .ENDS OUT_CURRENT_CLAMP .SUBCKT POWER_N_MOSFET drain gate source ****************************************************************************************** * WB_POWER_N_MOSFET Spice Model *C ****************************************************************************************** *General N-MOSFET Model 01/11/2010 *$ ************************************************************************************** **ALDD18** * Cgd = -> Gate to drain Capacitance fit to approximate gate charge * Cgs = -> Gate to source Capacitance * Cj0 = Cds -> Approximated Source to Drain Capacitance at Vds=0 (by given Coss at certain Vds) * VdsMax = 600.0 V -> Maximum drain to source Voltage * RdsON = (2 * 0.035 ) Ohms -> MOSFET on resistance * Rgate = 0.2 Ohms -> Gate Resistance * Vth = 1.5 V -> Threshold Voltage * Ciss =Cgd+ Cgs * Coss =Cds+ Cgd * Crss =Cgd Cgd g d 1E-12 M1 d g s s _M1_modX L=1u W=1u .MODEL _M1_modX NMOS CGDO=0 CGSO=0 KP=10 RD=0 RS=0 + TOX=1E-7 UO=400 VTO=1.5 Dnew Drain dx DIDEAL .model DIDEAL D Is=1e-12 N=0.145 Cjo=.1pF Rs=.0001 *Rds2 source s 0.0125 *Rds1 Dx d 0.0125 *Rds1 Drain d 0.035 Rds2 source s {0.0125*(1+0.0105*(T-27))} Rds1 Dx d {0.0125*(1+0.0105*(T-27))} RG gate g 0.2 Cgs g s 1.0E-9 Ileakage d s 10u *Ileakage d s 5m *Rleakage d s 68k Dbd source drain Dbt .MODEL Dbt D (BV= 600.0 CJO= 99E-15 Is=25e-12 M=0.35 N=11.27 VJ= 0.8 TT=10p Rs=0.00185 ) ** changed 99p to 99f so can be added to Var-CAP, N=11.27 to shift Vf to 7.8V & 10A X_S17 COMP_OUT 0 Drain DX Fake_SW_DIODE_S17 X_U103 VGS_INT N350958 COMP_OUT COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 + VTHRESH=0.5 V_V37 N350958 0 10 E_E1 VGS_INT 0 Gate Source 1 .ends POWER_N_MOSFET .subckt Fake_SW_DIODE_S17 1 2 3 4 S_S17 3 4 1 2 _S17 RS_S17 1 2 1G .MODEL _S17 VSWITCH Roff=1e6 Ron=7m Voff=0.0V Von=1.0V .ends Fake_SW_DIODE_S17 *.ENDS POWER_N_MOSFET .SUBCKT POWERMOS G D S PARAMS: RDSON=70m Ciss=1400p Crss=1p Coss=100p VSP=9 RG=0.2 * This is a simple model for Power MOSFET. * The parameters modeled are * - RDSon, * - Input Capacitance, * - Reverse capacitance, * - Output capacitance, * - Switching point voltage (Gate voltage where the FET starts switching), * - Gate Resistance C_C1 S Da {Coss} IC=0 R_R1 Da D 10 C_C2 Ga D {Crss} IC=0 R_R2 G Ga {RG} C_C3 Ga S {Ciss} IC=0 *D_D1 S Db Dbreak *R_R3 Db D 1m S_switchM D S Ga S _switchM RS_switchM Ga S 100Meg .MODEL _switchM VSWITCH Roff=100e6 Ron={RDSON} Voff=1.1 Von={VSP} .model Dbreak D Is=1e-14 Cjo=.1pF Rs=.1 .ends POWERMOS .SUBCKT Vds_Var_Cap Vds VCds E_MUX VCds 0 VALUE = {IF ( V(Vds) < = 10, 630e-12, + IF ( V(Vds) > 10 & V(Vds) < = 40, 350e-12, + IF ( (V(Vds) > 40 & V(Vds) < = 60) , ((-5p*V(Vds))+550p), + IF ( (V(Vds) > 60 & V(Vds) < = 130.000001) , 250e-12, + IF ( (V(Vds) > 130.0000011 & V(Vds) < = 150) ,((-7p*V(Vds))+1160p), 110e-12 ) ))))} .ENDS Vds_Var_Cap *.SUBCKT VI_HL Vin VDD Vout *E_out Vout 0 VALUE = {if ( V(Vin) > V(VDD)*0.7, V(VDD), *+ if ( V(Vin) < V(VDD)*0.3, 0 , V(VDD)/2 ))} *.ends VI_HL .SUBCKT VI_HL Vin Vout E_out Vout 0 VALUE = {if ( V(Vin) > = 2.5, 1, + if ( V(Vin) < = 0.8, 0 , 0.5 ))} .ends VI_HL .subckt Zener 1 2 D1 1 2 Zener_AL .MODEL Zener_AL D( IS=15N N=2.22 BV=19 IBV=14M RS=169M + CJO=4P VJ=750M M=330M FC=500M TT=100N + EG=1.11 XTI=3 KF=0 AF=1 ) .ENDS Zener