Tristate outputs in verilog

I am trying to simulate a tri-state latch in Verilog. It appears that the Verilog compiler doesn’t support it.

This is my code:

module vloglatch ( LE, D, OE, Q ) ;
// You will probably want to flush out the nature of these port declarations:
input wire LE;
input wire D;
input wire OE;
output reg Q;

reg latch; // Internal latch to store the value when LE is active

// Latch operation: Latch the input D at the rising edge of LE
always @(posedge LE) begin
latch <= D;

// Output operation: Drive Q with the latched value if OE is low, else high-impedance
always @(*) begin
if (OE == 1’b0) begin
Q <= latch;
end else begin
Q <= 1’bz; // High-impedance state when OE is high

And this is the error I received:

%Error-UNSUPPORTED: vloglatch.v:24:14: Unsupported tristate construct: ASSIGNDLY
** : … In instance vloglatch**
** 24 | Q <= 1’bz; **
** | ^~**
** … For error description see Errors and Warnings — Verilator Devel 5.017 documentation**
%Error: Exiting due to 1 error(s)
** … See the manual at Verilator User’s Guide — Verilator Devel 5.017 documentation for more assistance.**

Any ideas on how to go around this problem?

The top level module that interfaces to the SPICE side will not tristate. The only hope would be Verilog module to Verilog module.

Hi, @StanB.

I don’t do Verilog but it sounds like the problem that I’m starting to address here, (no tri-state micro-controller GPIO pin support in QSpice).

That is, QSpice C-Block code (which I think Verilog code ultimately compiles to) doesn’t have tri-state ports. There are input ports and output ports only. To implement GPIO requires three C-Block ports – one to read, one to set write output level, and one to control whether the output value is passed through to the GPIO.

As I write this, Mike just responded with “tri-state not implemented in QSpice.”

Assuming that this is the same problem, maybe my QSpice symbol will help get started. Ultimately, I’ll implement a simple class to make the GPIO pin look like a single QSpice port + control register.


And ‘Verilator’ doesn’t support tri-state.
As stated in the ‘Verilator Devel 5.017 documentation’, it says, ‘Verilator converts some simple tristate structures into two-state.’