sleep and wake up, regislters be reset

[color=#222222][size=small][font=Arial, Helvetica, sans-serif]hi, all:

we try to enter deep sleep, and spi cs wakeup it normally, but the registers be reset. we already config the AON enable, the following as:[/font][/size][/color]


for example, before sleep, the register config as follow:


enter sleep and wakeup:


I would recommend you check the sleep example from Decawave.



I like to expand on “Z’s” comment which states to look at the sleep example code.

Some questions recently posted related to eg sleep/waking up, double buffering, diagnostics could be answered/resolved by studying both the sample code itself and the notes on the bottom of the main.c .

Those of you who recently joined might not be aware that we have sample code API.
This API ,containing 25 examples of common operations, was released to aid design and development.

The 25 examples are:

1 ex_01a_simple_tx
2 ex_01b_tx_sleep
3 ex_01c_tx_sleep_auto
4 ex_01d_tx_timed_sleep
5 ex_02a_simple_rx
6 ex_02b_rx_preamble_64
7 ex_02c_rx_diagnostics
8 ex_02d_rx_sniff
9 ex_02e_rx_dbl_buff
10 ex_03a_tx_wait_resp
11 ex_03b_rx_send_resp
12 ex_03c_tx_wait_resp_leds
13 ex_03d_tx_wait_resp_interrupts
14 ex_04a_cont_wave
15 ex_04b_cont_frame
16 ex_05a_ds_twr_init
17 ex_05b_ds_twr_resp
18 ex_06a_ss_twr_init
19 ex_06b_ss_twr_resp
20 ex_07a_ack_data_tx
21 ex_07b_ack_data_rx
22 ex_08a_low_power_listen_rx
23 ex_08b_low_power_listen_tx
24 ex_09a_bandwidth_power_ref_meas
25 ex_09b_bandwidth_power_comp

The complete API can be downloaded from :


hi, Z and Leo:

I am researching the following code:

2 ex_01b_tx_sleep
3 ex_01c_tx_sleep_auto
4 ex_01d_tx_timed_sleep

but I want to know that what config must be awareable? for example wakeup/reset pin state? or the tx/rx interrupt pending must be cleared? or other?

the user manual don’t clearley describe them.and maybe what reason will reset the registers?

Hi Justin,

all interrupts must be cleared or device will not enter sleep
the wake up pin can be used to wake up the device (from sleep) if this is how you have configured the wake up option,
the reset pin should only be pulled low when wanting to reset the device, at all other times is should be tri-stated … never driven high… if the reset pin is not connected correctly (as per the design guide or data sheet) then you may reset the device inadvertently

hi, Z:

thanks, I will try it.

Hi everyone,
Related to the register reset on wake up, I noticed that the TX and Rx antenna delay value and the tx and Rx led control registers had to be reprogrammed upon wake-up. Is this usual behaviour?



TX/RX LEDs and TX antenna yes, but RX antenna is preserved.




I have been looking for the fastest possible reliable wakeup from deep sleep, but I am confused by the User Manual guidance on this.

User Manual (v2.12) says “It is also recommended to use the SLP2INIT or CPLOCK event status bits (in Register file: 0x0F – System Event Status Register) to drive the IRQ interrupt output line high to confirm the wake-up.”
I have used CPLOCK for this purpose and it seems to do the job, but I have some concern about how reliable it is (even though I have not noticed any problems so far). This is because the User Manual also says that “Note: The PLLLDT bit in Register file 0x24:00 –EC_CTRL should be set to ensure reliable operation of this CPLOCK bit.”
But I don’t understand how the PLLLDT bit can be ensured to be set when waking up from deep sleep since the EC_CTRL register is not maintained in the AON memory during deep sleep (according to Table 46 of the User Manual).

What is the correct way then to use the CPLOCK bit in device wakeup? Can CPLOCK be relied upon even if PLLLDT bit value might be lost during deep sleep?
Clearly I am missing something obvious since CPLOCK seems to work…