Love Qspice. Here is the question: I am designing a switched power supply for an electrical discharge machine. It uses FETS around 600 volts/40 amps rating. I have included parasitic inductances in the Qspice model (to the tune of like 3 to 10 nH which I think is representative of the layout. I get peak powers reported by Qspice sometimes in the multiple kilowatts but of duration of less than a 1us with a rep rate of 20 Khz. The kilowatts number frankly scare me and the data sheet for the FETs Safe Operating Area list D=0 i.e. non-repetitive. QSpice reports that the average power for these pulses is in the order of 6 watts and the prototype has heat sink and big fan and is running only a couple of degrees over ambient. How (or should) I think about this to get comfortable and/or what are “safe” peak powers?
Hi,
Are you speaking about peak instantaneous power? If so, you can use a B-source to compute the instantaneous power and plot it.
If you need a “windowed” average of peak power, this a a bit more difficult. This will require knowing the thermal rate of dissipation of the individual component(s) (probably your FET) and the thermal resistance of the attached PCB or heat sink.
Len
It is normal to see a kilowatt-level peak in instantaneous power during hard-switching operation. For example, if you run at 500V and 5A, the hard-switching peak can be 500V * 5A = 2.5kW. Regarding the SOA, what peak voltage, current and ton/toff (i.e. finite V and I are overlapping at ton or toff) are you seeing in your simulation, and what FET are you using?
This is link to the electrical discharge machine project QSpice simulation. The project is called Open_EDM. One of the things that makes it unique is the use of an inductor for energy storage. KSKelvin, maybe you can help me understand how to determine (in general power FET design) if a repetitive power pulse is cause for concern. Can one go from the Safe Operating Area datasheet curve which is for a single pulse (Dutycycle = 0) to a repetitive case? Is there a way to determine if a design has margin based on Qspice and datasheet?
well, the device in your schematic is IPW60R037CSFD, and here is Infineon datasheet : Datasheet IPW60R037CSFD
Diagram 2 is the SOA at case temperature of 25°C. It mentions DC, which, to my understanding, is what can be continuously applied without damaging the device. But the reading is only 4W @ Vds=100V for this a 245W max dissipation device? This greatly deviates from my understanding of SOA. Has the definition of SOA changed nowadays, or am I missing something?
Really missing a part. This is due to Thermal Instability Limit which related to Thermal Runaway characteristic, derating the SOA.
Application Note Linear Mode Operation and Safe Operating Diagram of Power MOSFETs
AKX00073-1 - Derating of the MOSFET Safe Operating Area
Understanding MOSFET datasheets: Safe Operating Area (SOA) | Video | TI.com
KSKelvin, thanks for the fast and detailed response. Let me see if I understand. The SOA in the datasheet is for D=0 i.e. one pulse/zero percent duty cycle. In my case (repetitive) you need to account for an increase in part temperature which derates the SOA. For very short pulses at relatively low switching frequencies i.e. very low duty cycle) the increase in temperature maybe quite small and the SOA at D=0 is pretty close to the story.
Yes, the SOA assumes no other contributor raises the junction temperature. D=0 means removing conduction loss from the equation, and the SOA is purely a stress study of the FET in the linear region.
Other losses will derate the SOA as those dissipations contribute to raising the junction temperature.
If go over your simulation, the switching loss during the ON transition lasts about 50ns. The peak current is 170A at 100V, meaning it is within the 1us SOA region at case temperature of 25°C.
Just beware that such a high di/dt is not good, as it may introduce serious EMI or inject noise into the gate loop.
KSKelvin…thanks for taking the time to run the simulation. I understand your concern about EMI and adding noise to the gate drive. We (actually the guy who did most of the design) took great pains on the layout to make the gate drive more immune. If I understand correctly, the gate drive resistor gives me a handle on the di/dt (of course with other tradeoffs). I actually have a prototype of the circuit running at 48 volts (not the full 144 volt design goal…I screwed up the pcb trace spacings so this first prototype may not hold off 144 volts so I starting off at 48. It cuts metal and everything, included FETs are pretty close to ambient. So far no failures (fingers crossed).