DIS_FCE, DIS_PHE, and DIS_RSDE are 3 bits belonging to register 0x04 (SYS_CFG).
I was wondering what the chip does when setting those 3 bits to 1.
1- DIS_FCE: Disable frame check error handling. I understand that in case of CRC error I can still access the DATA part of the packet from the memory.
2- DIS_PHE: Disable receiver abort on PHR error. It is not clear to me how the chip would continue decoding the packet on PHR error (PHE). Would the data be available in the memory so I can read it directly and perform manual decoding (like FCE)?
3- DIS_RSDE: Disable Receiver Abort on RSD error. It is not clear to me how the chip would continue decoding the packet on Reed Solomon error. Would the data be available in the memory so I can read it directly and perform manual decoding (like FCE)?