To include a verilog block in a schematic on have to
- Draw a hierarchical Entry
- change the Symbol Type,
- Add Ports
- Define their Data Type and Port Type
- Create Verilog Template
- Compile Verilog to C++
In step 5, the tool automatically creates a .v and .cpp.
The following example shows a simple design with “Xs” and “Ys” ports
if the pin names include any capital letters, they turn into normal letters.
Then the compilation fails.
If you want to keep the capital letters you need to change them manually and it works perfectly.
This could be an issue when importing an existing large verilog design with a mixture of them like “SamplingEnable” for instance, which is common practice.
Is there a way to avoid this in the automatic generation?
Sergio