Plans for an extra PWL Kernel (Katzenelson-style)?

Dear Mike E.,
are there plans to add time stepping for piecewise-linear devices, truncated symbolic laplace circuit response, as described by Katzenelson and Bell Labs, and sold by e.g. SIMPLIS ? (This could be restricted to a subset, or separate set, of devices, and pre-characterisation of the silicon cards.)

I don’t know what you mean by, “truncated symbolic Laplace circuit response”, but QSPICE does Laplace. For time domain, it synthesizes a circuit. But if synthesis fails, it won’t integrate the impulse response. I’ve never been happy with that method.

The mention of Laplace is muddying the question. What I meant to ask is whether a PWL kernel is in any (blue sky) plan. Example: Hierarchical symbolic piecewise-linear circuit analysis | IEEE Conference Publication | IEEE Xplore

I think these days, with the right numerical methods underneath, one can just go straight to the full SPICE/mixed-mode simulation. Doing a full, literal, simulation is usually less error prone in the overall design flow.