Issue with a Verilog output pin

I’m starting with Verilog, so I may be just doing something silly here, but the code I’ve posted here does not output 1 on the error output pin. All the rest of the logic seems to work fine, but I was trying to do a math operation and output the result on error and I wasn’t getting anything. So I tried a few different things, and ultimately, I tried just assigning the number 1 to it to see if at least that would work, but it didn’t so I assume there is something silly I’m doing here.

module fpga (clk, in, fb, h_sw, l_sw, error);
   input wire clk;
   input wire in;
   input wire fb;
   output reg h_sw, l_sw;
   output reg error;

   always @(posedge clk)

        if(in > fb)
            h_sw <= 1;
            l_sw <= 0;
            l_sw <= 1;
            h_sw <= 0;

      error <= 1'b1;


If you guys don’t see anything that may be the issue right away, I’d be happy to upload the schematic file to a server and share the link.

Any help is appreciated.