Hello everyone, is it possible to create two isolated grounds in a SPICE simulation? I’d like to isolate the GND both of driver and power of this circuit. Thank you.
isolated_GND.qsch (4.4 KB)
The symbol you used — the onsemi SiC Cascode JFET Level=2010 symbol — has been removed from Qspice lately.
You can have a signal ground (SGND) and a power ground (PGND) in this circuit, but they are not isolated, as KS and S are basically connected inside the device (though not with zero impedance). In this application, SGND and PGND is for signal current return to SGND and power current return to PGND. In simulation, GND is 0V. In this case, you can assign the net name “SGND” to all signal grounds and add a 1G resistor between this SGND and the 0V potential. GND will now act as PGND. In SPICE, all nodes need to have a finite impedance path to 0V (I think this is also true in real-world applications; isolation only means very high DC impedance between two nodes).
example.UF3SC120009K4S.qsch (5.1 KB)
2 Likes
Or, you ask for this?
example.UF3SC120009K4S-ISO.qsch (6.6 KB)
1 Like
Hi Kelvin, thank you for the well explanation. I prefer this one as I’d use an isolated gate driver in real hardware.
I am a bit confuse as if you are looking for isolated gate driver, it represents my 2nd reply (https://forum.qorvo.com/t/isolated-gnd-simulation/26292/3), or something like this. For example, we need isolation as signal and power both reference to ground, but as Source is floating in this case, isolation is required to allow floating gate drive.
You know the KS (Kelvin Source) pin of the SiC Cascode is not isolated, right? It only serves as a gate return path. KS and S separate the return path of gate and drain, but they somehow connect in the package (expect to have same potential).
example.UF3SC120009K4S-ISO-Xfmr.qsch (8.2 KB)
