Hi,
i wanted to make shure if my understanding is correct and that this should work in theory or
if there is general thing that i have missed here.
My current setup: 3 x DWS3000 (2 configured as a Anchor and 1 as a Tag).
Tag configuration:
The tag DWS3000 is sending a broadcast message and expecting a response:
dwt_starttx(DWT_START_TX_IMMEDIATE | DWT_RESPONSE_EXPECTED);
After the transmission is successful sent out we are waiting for a response message.
If the RXFCG Bit is true we copy it to our local buffer.
After copying to our local buffer we clear the SYS Status Register Bits RXPRD, RXSFDD,CIADONE,RXPHD (Bits 8 to 11) with
dwt_write32bitreg(SYS_STATUS_ID,0xf00);
Now we are looking for the next response message until the RXFCG Bit is true or a error occurs:
while (!((status_reg = dwt_read32bitreg(SYS_STATUS_ID)) & (SYS_STATUS_RXFCG_BIT_MASK | SYS_STATUS_ALL_RX_ERR)))
{ };
Once again if the RXFCG Bit is true we copy it to our second local buffer and after that we are clearing
SYS Status Register Bits RXPRD, RXSFDD,CIADONE,RXPHD (Bits 8 to 11) and TXFRB, TXPRS, TXPHS, TXFRS (Bits 4 to 7) with
dwt_write32bitreg(SYS_STATUS_ID,0xff0);
After that we start again with a Poll message
Anchor 1 configuration:
We listening for some broadcast messages until an error occurs or the RXFCG Bit is true:
while (!((status_reg = dwt_read32bitreg(SYS_STATUS_ID)) & (SYS_STATUS_RXFCG_BIT_MASK | SYS_STATUS_ALL_RX_ERR )))
{
};
We transfer the recieved message to our local buffer
We set our delay_time for Anchor 1 and sent the response with our configured Delay until the SYS_STATUS_TXFRS_BIT_MASK is set to 1.
We clear the recieve and transmit registers with
dwt_write32bitreg(SYS_STATUS_ID,0xff0);
and start again to listen for new messages
Anchor 2 configuration:
We listening for some broadcast messages until an error occurs or the if the RXFCG Bit is true:
while (!((status_reg = dwt_read32bitreg(SYS_STATUS_ID)) & (SYS_STATUS_RXFCG_BIT_MASK | SYS_STATUS_ALL_RX_ERR )))
{
};
We transfer the recieved message to our local buffer
We set our delay_time for Anchor 2 with a longer delay than Anchor 1 to make shure the messages will send out one after the other.
Last step is to check until SYS_STATUS_TXFRS_BIT_MASK is set to 1 then
we clear the recieve and transmit registers with
dwt_write32bitreg(SYS_STATUS_ID,0xff0);
and start again to listen for new messages
Will this work in theory?
Thanks in advance
David