Hi everyone, I have been investigating this phenomenon. May I ask @shijomts and @chuanqi about your timings for reading the registers, particularly 0x12? I noticed that depending on the order of data reading and other status register readings, I got a different average duration between CIR_PWR = 0, for a given rate of message reception.
For example, I am sending a 1 byte payload every 20 milliseconds. I have encountered some strange issues with bits in the status register not being set immediately after the interrupt fires, for such a small payload. So I introduce a delay before reading the status register. If I make that delay longer, the average duration between CIR_PWR = 0 events initially increases but does not seem to stay stable.
I’m going to do some more tests but please share any more information about your setup that may help identify the cause of this behaviour, in the meantime.