Cannot clear SYS_STATUS register flags

Hello,

I’m using a particular DW1000 chip for receiving in double buffer mode, with RXAUTR set.
I implemented a state machine strictly based on the flow chart in the User Manual 4.3.3.
Everything works fine, until I come to a point where SYS_STATUS register flags need to be cleared.
I just cannot do that. No matter how hard I try, the content of the register won’t change.

Even if I apply TRXOFF, and then do an RX-only reset, it won’t work.
It works only at startup, before I put the chip in RX mode.

I’m constantly monitoring the SYS_STATE(0x19) register, and everything seems fine.
I apply TRXOFF, the chip goes to IDLE state, and I’m still unable to clear SYS_STATUS.

Please help me on this, the Application Notes and User Manual do not cover this issue.

Regards,
Levente

Dear lev_szucs,

did you solve your issue?

I have similar problems when using double buffer mode (but without “auto rx enable”, meaning RXAUTR=0). When I stress my system by flooding them with too many packets in order to trigger a double buffer overflow I am not able anymore to clear some event bits in SYS_STATUS register. This make my system stuck because the deca interrupt cannot be de-asserted anymore.

regards

spachner

Please study the double buffer example from API/simple examples package from Decawave.

Let us know if you find issues with the example code.

Note if you use manual re-enable (auto should not be used) you cannot get overrun.

Z

Hi Zoran,

thanks for replying. The double buffer example ist straight forward. Yes, your are right, when using manual re-enable overrun cannot happen.

There is still something in question:
In the Deca examples the DW1000 interrupt is configured rising edge triggered rather than level triggered.

Imagine when while executing the dwt_isr() the other receive buffer gets full right before the isr comes to the line where the DW1000 interrupt should be de-asserted for the first received packet.

// The DW100 interrupts should be de-asserted, this is done by executing: if (pdw1000local->dblbuffon) { // Toggle the Host side Receive Buffer Pointer dwt_write8bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_HRBT_OFFSET, 1); }

The interrupt line of DW1000 would stay asserted then, since the other buffers’s interrupts is already active. Then the second packet will be lost, since the mcu will not recognize the 2nd interrupt since there is no rising edge. System stucks.

I would say double buffer reception is only reliable when using mcu level interrupts. What is your opinion?

regards

spachner

Hi Zoran,

thanks for replying. The double buffer example ist straight forward. Yes, your are right, when using manual re-enable overrun cannot happen.

regards

spachner