Might be best to talk to this guy: mike.engelhardt@qorvo.com
If it can be implemented, I would use it. IMO I would rather write Verilog for simulations than C++ because it ports directly to an FPGA. I have been using the current Verilog implementation but I have to drive the Verilog block with a 1GHz pulse which forces the simulation to generate sub ns steps and the whole thing runs slow. Also have to simulate the delay (filter and comparator) on the outputs of the FPGA.