Thank you!
Later I’ve found this topic - " [Github code for dwm1001-dev can’t change source and dest](Github code for dwm1001-dev can't change source and dest) "
and understand, that chip “MAC-level support” adressing functions is limited just to address comparison (for irq). And I must set MPDU myself in packet payload.
About IRQ error packets.
Have you tried setting the interrupt mask without handling bad packets?
“Register file: 0x0E – System Event Mask Register”
MRXFCG reg:0E:00 bit:14
Mask receiver FCS good event. When MRXFCG is 0 the RXFCG event status bit will not
generate an interrupt. When MRXFCG is 1 and the RXFCG event status bit is 1, the
hardware IRQ interrupt line will be asserted to generate an interrupt.MRXFCE reg:0E:00 bit:15
Mask receiver FCS error event. When MRXFCE is 0 the RXFCE event status bit will not
generate an interrupt. When MRXFCE is 1 and the RXFCE event status bit is 1, the
hardware IRQ interrupt line will be asserted to generate an interrupt